/ Pinocchio Geometry Operation
// Copyright(c) Fujitsu Limited ALL RIGHTS RESERVED
//
// Macro Definition
// Ver 0.4 Start on 14th May 1997 E.Miura
//

//	# : the value is broken

//----------------------------------------------------------------
//	Bank Control
//----------------------------------------------------------------

.macro	SetBank		bO,bP,bI
		ld		#((\bO<<2)|(\bP<<1)|(\bI)),ctr
.endm

.macro	SetBankAll	bank
//	#r15			CTR data
//	#r14			mask
		mov		ctr,r15
	.if \bank
		ld		#7,r14			// r14:0x00000007
		or		r14,r15
	.else
		ld.in	#-8,r14			// r14:0xFFFFFFF8
		and		r14,r15
	.endif
		mov		r15,ctr
.endm

.macro	SetBank1	flag
//	#r15			CTR
//	#r14			mask
		ld		#\flag,r14
		mov		ctr,r15
		or		r14,r15
		mov		r15,ctr
.endm

.macro	SetBank0	flag
//	#r15			CTR
//	#r14			mask
		ld		#-1,r15
		ld		#\flag,r14
		exor	r15,r14
		mov		ctr,r15
		and		r14,r15
		mov		r15,ctr
.endm

//----------------------------------------------------------------
//	External address calclation
//----------------------------------------------------------------

.macro	RtoBRAR	r,br,ar
//	#r15			tmporary address
		mov		\r,r15
		mov		\r,\ar
		lsr		#8,r15
		lsr		#8,r15
		mov		r15,\br
.endm

//----------------------------------------------------------------
//	Load Store
//----------------------------------------------------------------

.macro	STIOii		data,adr
//	#ar7			io address
//	br1				io base address
//	#r15			imm data
		ld.ih		#\adr,ar7
		ld			#\data,r15
		st			r15,br1(ar7)
.endm

.macro	STINTri		reg,adr
//	#ar7			imem address
		ld.ih		#\adr,ar7
		st			\reg,0x0(ar7)
.endm

.macro	STEXTrr	reg,breg,areg
		st			\reg,\breg(\areg)
.endm

.macro	STEXTPrr	reg,breg,areg
		st			\reg,\breg(\areg)
		adda		#4,\areg
.endm

.macro	STEXTMrr	reg,breg,areg
		st			\reg,\breg(\areg)
		suba		#4,\areg
.endm

.macro	LDIOi		adr,reg
//	#ar7			io address
		ld.ih		#\adr,ar7
		ld			br1(ar7),\reg
.endm

.macro	LDINTi		adr,reg
//	#ar7			internal mem address
		ld.ih		#\adr,ar7
		ld			0x0(ar7),\reg
.endm

.macro	LDEXTPr		breg,areg,reg
		ld			\breg(\areg),\reg
		adda		#4,\areg
.endm

.macro	LDEXTr		breg,areg,reg
		ld			\breg(\areg),\reg
.endm

.macro	DebugPush	reg
		push	\reg
.endm
.macro	PushAllReg
		DebugPush	r0
		DebugPush	r1
		DebugPush	r2
		DebugPush	r3
		DebugPush	r4
		DebugPush	r5
		DebugPush	r6
		DebugPush	r7
		DebugPush	r8
		DebugPush	r9
		DebugPush	r10
		DebugPush	r11
		DebugPush	r12
		DebugPush	r13
		DebugPush	r14
		DebugPush	r15
//
		DebugPush	fr0
		DebugPush	fr1
		DebugPush	fr2
		DebugPush	fr3
		DebugPush	fr4
		DebugPush	fr5
		DebugPush	fr6
		DebugPush	fr7
		DebugPush	fr8
		DebugPush	fr9
		DebugPush	fr10
		DebugPush	fr11
		DebugPush	fr12
		DebugPush	fr13
		DebugPush	fr14
		DebugPush	fr15
//
		DebugPush	ar0
		DebugPush	ar1
		DebugPush	ar2
		DebugPush	ar3
		DebugPush	ar4
		DebugPush	ar5
		DebugPush	ar6
		DebugPush	ar7
//
		DebugPush	br0
		DebugPush	br1
		DebugPush	br2
		DebugPush	br3

.endm		
//----------------------------------------------------------------
//	DMA control
//----------------------------------------------------------------

.macro	StartDMA	channel
//	r15				dummy (don't care of its contents)
//	br1				IO base address
//	#ar7			DMA register address
	.if \channel
		ld.ih		#_DMAO_OFFSET+_DMA_DMCR,ar7
	.else
		ld.ih		#_DMAI_OFFSET+_DMA_DMCR,ar7
	.endif
		stub		r15,br1(ar7)
.endm

.macro	WaitDMA		channel
//	#r15			DMA Status Register
//	#r14			Flag Mask
//	br1				IO base address
//	#ar7			DMA register address
	.if \channel
		ld.ih		#_DMAO_OFFSET+_DMA_DSR,ar7
	.else
		ld.ih		#_DMAI_OFFSET+_DMA_DSR,ar7
	.endif
		ld			#4,r14
WaitDMALoop\@:
		ldub		br1(ar7),r15
		and			r14,r15
		bnz			WaitDMALoop\@
		nop
.endm

.macro	SetDMAMode	channel
//	#r15			Work
//	br1				IO base address
//	#ar7			DMA register address
//	reset
	.if \channel
		ld.ih		#_DMAO_OFFSET+_DMA_DCR,ar7
	.else
		ld.ih		#_DMAI_OFFSET+_DMA_DCR,ar7
	.endif
		stub		r15,br1(ar7)
//	set DMA mode
	.if \channel
		ld.ih		#_DMAO_OFFSET+_DMA_DXBE,ar7
	.else
		ld.ih		#_DMAI_OFFSET+_DMA_DXBE,ar7
	.endif
		lduh		#(b_DMA_EOT | b_DMA_NOINT)<<8 | 0x0,r15
		stuh		r15,br1(ar7)
.endm

.macro	SetDMArii	channel,regsa,da,count
//	#r15			Work
//	br1				IO base address
//	#ar7			DMA register address
//	set S adrs 
	.if \channel
		ld.ih		#_DMAO_OFFSET+_DMA_BAR,ar7
	.else
		ld.ih		#_DMAI_OFFSET+_DMA_BAR,ar7
	.endif
		st			\regsa,br1(ar7)
//	set D adrs
		adda		#4,ar7
		ld			#\da,r15
		st			r15,br1(ar7)
//	set xfer count
		adda		#4,ar7
		ldub		#\count,r15		//!! count < 256
		st			r15,br1(ar7)
.endm

.macro	SetDMArri	channel,regsa,regda,count
//	#r15			Work
//	br1				IO base address
//	#ar7			DMA register address
//	set S adrs 
	.if \channel
		ld.ih		#_DMAO_OFFSET+_DMA_BAR,ar7
	.else
		ld.ih		#_DMAI_OFFSET+_DMA_BAR,ar7
	.endif
		st			\regsa,br1(ar7)
//	set D adrs
		adda		#4,ar7
		st			\regda,br1(ar7)
//	set xfer count
		adda		#4,ar7
		ldub		#\count,r15		//!! count < 256
		st			r15,br1(ar7)
.endm

//----------------------------------------------------------------
//	Conditional Branch
//----------------------------------------------------------------

.macro	BEQr		reg,val,adr
		ldub		#\val,r15
		cmp			r15,\reg
		bz			\adr
		nop
.endm

//----------------------------------------------------------------
//	Floating point operation
//----------------------------------------------------------------

.macro	FRCP32
//	#fr15			Input
//	#fr14			Result
//	#fr15-fr11		work
		frcp		fr15,fr14			//	fr14=Xi
		mov			fr15,fr13			//	fr13=a
		ld			#0f2.0,fr12			//	fr12=2.0
		fmul		fr14,fr13			//	fr13=a*Xi
		mov			fr12,fr11			//	fr11=2.0
		fsub		fr13,fr12			//	fr12=2.0-a*Xi
		fmul		fr12,fr14			//	fr14=Xi+1
		fmul		fr14,fr15			//	fr5=a*Xi+1
		fsub		fr15,fr11			//	fr11=2.0-a*Xi+1
	.if MB86240		//..............................
		nop
	.endif
		fmul		fr11,fr14			//	fr14=Xi+2
.endm

.macro	FSQRRCP32
	//	fr15	:	Input
	//	fr14	:	Result
	//	fr15-11	: work
		fsqr		fr15,fr14			//	fr14=Xi
.if 1
		mov			fr15,fr13			//	fr15=fr13=a
		fmul		fr14,fr13			//	fr13=a*Xi
		fmul		fr14,fr13			//	fr13=a*Xi^2
		ld			#0f3.0,fr12
		fsub		fr13,fr12			//	fr12=3.0-a*Xi^2
		fmul		fr12,fr14			//	fr14=Xi*(3.0-a*Xi^2)
		ld			#0f0.5,fr11
		fmul		fr11,fr14			//	fr14=Xi+1=0.5*Xi*(3.0-a*Xi^2)
		fmul		fr14,fr15			//	fr15=a*Xi+1
		fmul		fr14,fr15			//	fr15=a*Xi+1^2
		ld			#0f3.0,fr12
		fsub		fr15,fr12			//	fr12=3.0-a*Xi+1^2
		fmul		fr12,fr14			//	fr14=Xi+1*(3.0-a*Xi+1^2)
		fmul		fr11,fr14			//	fr14=Xi+2=0.5*Xi+1*(3.0-a*Xi+1^2)
.endif
.endm

.macro	Trans3D		arP,arI,regx,regy,regz
		fmacm		0:0(\arP),(\arI)
		fmacm		1:0(\arP),(\arI)
		fmacm		2:0(\arP),(\arI)
		fmacm		0:1(\arP),(\arI)
		fmacm		1:1(\arP),(\arI)
		fmacm		2:1(\arP),(\arI)
		fmacm		0:2(\arP),(\arI)
		fmacm		1:2(\arP),(\arI)
		fmacm		2:2(\arP),(\arI)
		fmacm		0:3(\arP),(\arI)
		fmacm		1:3(\arP),(\arI)
		fmacm		2:3(\arP),(\arI)
		mova		raccx,\regx
		mova		raccy,\regy
		mova		raccz,\regz
.endm

.macro	Trans		arP,arI,regx
	//	#arP	:	P-ram pointer
	//	#arI	:	I-ram pointer
		fmac			(\arP)+,(\arI)+
		fmac			(\arP)+,(\arI)+
		fmac			(\arP)+,(\arI)+
		fmac			(\arP)+,(\arI)+
		fsum			\regx
.endm

.macro	ColClip		reg
	//	fr15	:	Clip Value
		fcmp	fr15,\reg
		ble		ColNoClip\@
		nop
		mov		fr15,\reg		
	ColNoClip\@:
		nop
.endm
//----------------------------------------------------------------
//	D3D
//----------------------------------------------------------------

.macro	GetInst	reg
	//	#r15	:	instruction address
	//	#r14	:	instruction address update
	//	#ar7	:	instruction address pointer
	//	#br3	:	instruction base address
		ld.ih		#_P0_pINSTRUCTION,ar7
		ld			0x0(ar7),r15
		mov			r15,r14
		add			#4,r14
		st			r14,0x0(ar7)
		RtoBRAR		r15,br3,ar7
		ld			br3(ar7),\reg
.endm

.macro	IndexCmp	regold,regnew,idxold,idxnew
		cmp			\regold,\regnew
		bnz			IndexCmp\@
		nop
		mov			ir\idxold,ar\idxnew
		add			#1<<\idxold,r11
		add			#1<<\idxnew,r12
	IndexCmp\@:
.endm