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Date: Tue, 18 Nov 2008 20:13:09 -0800
From: Andrew Sharp <andy.sharp@onstor.com>
To: Bill Fisher <bfisher@onstor.com>
Cc: Brian Stark <brian.stark@onstor.com>
Subject: Re: BCM 1480 Mailbox Register Address'es and Offset
Message-ID: <20081118201309.2f532f00@ripper.onstor.net>
References: <49238591.7040500@onstor.com>
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OK,

Seriously Bill you can leave this sort of system detail to me, as I
will make sure this stuff is all hooked up and working by the time we
need it.  If there is some problem like we don't have something wired
up like we need, then we'll have to live with that and use polling or
something.  No biggie.

On Tue, 18 Nov 2008 19:18:41 -0800 Bill Fisher <bfisher@onstor.com>
wrote:

> Guys:
> 
> In the Linux kernel header file, include/asm/sibyte/bcm1480_regs.h
> we find the following mappings;
> 
> /*
> *********************************************************************
>      * System Interrupt Mapper Registers (Sections 4.3-4.5)
>  
> *********************************************************************
> */
> 
> #define A_BCM1480_IMR_CPU0_BASE             0x0010020000
> #define A_BCM1480_IMR_CPU1_BASE             0x0010022000
> #define A_BCM1480_IMR_CPU2_BASE             0x0010024000
> #define A_BCM1480_IMR_CPU3_BASE             0x0010026000
> #define BCM1480_IMR_REGISTER_SPACING        0x2000
> #define BCM1480_IMR_REGISTER_SPACING_SHIFT  13
> 
> 
> /*
>   * these macros work together to build the address of a mailbox
>   * register, e.g.,
>   *   A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2)
>   * for mbox_0_set_cpu2 returns 0x00100240C8
>   */
> #define R_BCM1480_IMR_MAILBOX_CPU         0x00
> #define R_BCM1480_IMR_MAILBOX_SET         0x08
> #define R_BCM1480_IMR_MAILBOX_CLR         0x10
> #define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20
> 
> #define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \
>      (A_BCM1480_IMR_CPU0_BASE + \
>       (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \
>       (cpu * BCM1480_IMR_REGISTER_SPACING) + \
>       (R_BCM1480_IMR_MAILBOX_0_CPU + reg))
> 
> Using the above macro we get the following:
> A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,0)
> 
> For CPU 0 we get the 40-bit address: 0x00 1002 0008
> for Mailbox 0 on cpu 0.
> 
> On the TxRx the physical address is: 0x10 7000 0008
> for the cpu 0 set register, which is being used
> today to generate the SSC mailbox 0 interrupt.
> 
> This is as per our conversation this afternoon,
> and as per Brian's mail containing the
> mapping for the PCI access for
> the different processors to the mailboxes:
> 
> SSC Mailbox		0x7000.0000
> TXRX Mailbox		0x8000.0000
> FP Mailbox		0x9000.0000
> 
> The upper 8-bits of the physical address for
> the PCI access is:
> 
> SSC	0xF8
> TxRx	0x10
> FP	0x10
> 
> On the TxRx the value EEE is using is:
> 0x1070000008UL
> 
> On the SSC, the value I mam proposing to
> use is:
> 
> 0xF880000008UL
> =========================
> 
> Hence the Linux kernel must be adjusted
> to either add the proper top 8-bits
> and get the CPU0_BASE to be defined
> properly.
> 
> Questions:
> 
> 1) Hence can we "adjust" the map on the TxRx Linux
> kernel to "fix" this or do we redefine the
> A_BCM1480_IMR_CPU0_BASE value?
> 
> 2) Do we look at the stock ARC prom code supplied
>     by the SDK packages for the various development
>     boards to see what they use for the map?
> 
> Thanks,
> 
> -- Bill
> 
> PS: Lunch is hanging in the balance.
> 
> 
> 
> 
> 
> 
