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Subject: RE: assignments & settings for TI part
Date: Tue, 8 May 2007 11:10:46 -0700
Message-ID: <BB375AF679D4A34E9CA8DFA650E2B04E03994D72@onstor-exch02.onstor.net>
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Thread-Topic: assignments & settings for TI part
Thread-Index: AceRj9smCE31LO9lRTKcmKZcr+9+fgAC11hw
From: "Warren Gale" <warren.gale@onstor.com>
To: "Andy Sharp" <andy.sharp@onstor.com>,
	"Brian Stark" <brian.stark@onstor.com>


Andy,
  I went and looked at the bsd stuff.. It sparked some
memories that I had forgotten.
If memory server me correct, the routine "pci_wait_fifo()"
would cause accesses to hang forever.....

In file:
  "src/sys/dev/pci/i82365_pci.c"


void pcic_wait_fifo(void)
{
#ifdef BOBCAT
        if (is_cf_vendor_TI)
                return;
#endif
        while (!(pcic_read(&pcic_sc->handle[0], 0x17) & 0x80));
        while (!(pcic_read(&pcic_sc->handle[1], 0x17) & 0x80));
}
-------------------------------------------------------------
In the same file right below that function there are lots of
stuff that has address in it..
    is_cf_vendor_TI) {
                sc->ioh =3D 0xb8010000
     #ifdef BOBCAT
        if (bus_space_map(memt, 0x18800000, 0x10000, 0, &memh))

-------------------------------------------------------------


void
pcic_pci_attach(parent, self, aux)
        struct device *parent, *self;
        void *aux;
{
        struct pcic_softc *sc =3D (void *) self;
        struct pcic_pci_softc *psc =3D (void *) self;
        struct pcic_handle *h __attribute__((unused));
        struct pci_attach_args *pa =3D aux;
        pci_chipset_tag_t pc =3D pa->pa_pc;
        bus_space_tag_t memt =3D pa->pa_memt;
        bus_space_handle_t memh;
        bus_size_t size;
        int irq;
        int i __attribute__((unused));
        uint8_t r;

        pcic_sc =3D sc;

#ifdef BOBCAT
        if (is_cf_vendor_TI) {
                sc->ioh =3D 0xb8010000;
                sc->iot =3D pa->pa_iot;
                goto skip;
        }
#endif
        if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0,
            &sc->iot, &sc->ioh, NULL, &size)) {
                printf(": can't map i/o space\n");
                return;
        }
#ifdef BOBCAT
skip:
#endif
        /* Map mem space. */
#if defined(GALILEO_REAL_SSC)
#ifdef BOBCAT
        if (bus_space_map(memt, 0x18800000, 0x10000, 0, &memh)) {
#else
        if (bus_space_map(memt, 0x15800000, 0x10000, 0, &memh)) {
#endif
#else
        if (bus_space_map(memt, 0x120d0000, 0x10000, 0, &memh)) {
#endif
                printf(": can't map mem space");
                bus_space_unmap(sc->iot, sc->ioh, size);
                return;
        }

#if defined(GALILEO_REAL_SSC)
#ifdef BOBCAT
        sc->membase =3D 0x18800000;
#else
        sc->membase =3D 0x15800000;
#endif
#else
        sc->membase =3D 0x120d0000;
#endif
        sc->subregionmask =3D (1 << (0x10000 / PCIC_MEM_PAGESIZE)) - 1;

        /* same deal for io allocation */

        sc->iobase =3D 0x400;
        sc->iosize =3D 0xbff;
    .
    .
    .
    .
    .



Is this what you are looking for ????

Thanks,
Warren



-----Original Message-----
From: Andy Sharp=20
Sent: Tuesday, May 08, 2007 9:42 AM
To: Brian Stark
Cc: Warren Gale
Subject: Re: assignments & settings for TI part

I think I stated exactly what documentation I'm looking for, didn't
I?  The email snippets quoted here would highly suggest that in fact it
does not work exactly like the other part, so I don't know why you keep
saying that.  Maybe I don't understand something, but it sounds like
the interrupts are reversed, and the part does request PCI MEM
resources, unlike the Cirrus part, so that's different too.

Am I being dense?  I know I'm just an ignorant software engineer, so
help me out here.

a

On Tue, 8 May 2007 09:15:18 -0700 "Brian Stark"
<brian.stark@onstor.com> wrote:

> Andy,
>=20
> What kind of documentation are you looking for?  The part works just
> like the old one, and we can change that if needed.
>=20
>=20
> Brian
>=20
>=20
> -----Original Message-----
> From: Andy Sharp
> To: Warren Gale
> CC: Brian Stark
> Sent: Tue May 08 08:29:48 2007
> Subject: Re: assignments & settings for TI part
>=20
> Whipping out my French/English dictionary, I find that I cannot
> translate any of this.  Darn.
>=20
> So, what I'm hearing is that we don't have this properly documented
> anywhere, and in BSD just the bare minimum was done to make it use the
> pd6729 driver in compatibility mode, with the same performance
> deficiencies.
>=20
> I did try swapping the irqs and using irq11 for slot 1 and irq10 for
> slot 2, but that gave the same results.  Just in case the French
> words below were saying I should do that.
>=20
> On Mon, 7 May 2007 18:19:41 -0700 "Warren Gale"
> <warren.gale@onstor.com> wrote:
>=20
> > Andy,
> >   Dan did some changes that are in BSD drivers for the TI Part.
> > If I remember right we look at the ID and do some different stuff
> > depending on which part is there...
> >=20
> >=20
> > There was something in an e-mail thread about interrupts.
> >  > Dan, the TI controller can only map socket A interrupts to INTA_L
> >  > and
> >=20
> >  > socket B interrupts to INTB_L.  This is basically reversed from
> >  > the old Bobcat since we program the Intel controller to generate
> >  > socket A
> >=20
> >  > interrupts on PCI INTB_L / PMC INT8_L and socket B interrupts on
> >  > PCI INTA_L / PMC INT9_L.  On the new board, we have to reverse
> >  > the interrupts inside the PMC.  Can you build a BSD image that
> >  > looks for socket A interrupts on PCI INTA_L / PMC INT9_L (IM11)
> >  > and socket B interrupts on PCI INTB_L / PMC INT8_L (IM10)?
> >  >
> >=20
> > Here is the change list numbers and the files Dan modified to=20
> > get it to work with BSD.
> >=20
> >=20
> > Change List #'s  21194, 21246
> >=20
> > Files:
> >
//depot/R1_3_3_work/openbsd/src/sys/arch/pmonmips/pci/pcic_pci_machdep.c
> > #4 edit
> >
//depot/R1_3_3_work/openbsd/src/sys/arch/pmonmips/pmonmips/kgdb_machdep.
> > c#4 edit
> >
//depot/R1_3_3_work/openbsd/src/sys/arch/pmonmips/pmonmips/machdep.c#4
> > edit
> > //depot/R1_3_3_work/openbsd/src/sys/dev/ic/i82365.c#4 edit
> > //depot/R1_3_3_work/openbsd/src/sys/dev/pci/i82365_pci.c#4 edit
> > //depot/R1_3_3_work/openbsd/src/sys/dev/pci/pci.c#4 edit
> > //depot/R1_3_3_work/openbsd/src/sys/dev/pci/pcidevs.h#4 edit
> > //depot/R1_3_3_work/openbsd/src/sys/dev/pci/pcidevs_data.h#4 edit
> >=20
> > Hope this helps :)
> > Warren
> >=20
> > -----Original Message-----
> > From: Brian Stark=20
> > Sent: Monday, May 07, 2007 5:27 PM
> > To: Andy Sharp
> > Cc: Warren Gale
> > Subject: Re: assignments & settings for TI part
> >=20
> > Andy,
> >=20
> > The mem map and interrupts are configured in prom and are set up
> > identically to the Intel part.  Let me dig through some old emails
> > to see if Dan did anything differently in bsd.  If not, then prom
> > will serve as the best example, and Warren can help answer
> > questions.
> >=20
> >=20
> > Brian
> >=20
> >=20
> >=20
> > -----Original Message-----
> > From: Andy Sharp
> > To: Brian Stark
> > Sent: Mon May 07 17:05:10 2007
> > Subject: assignments & settings for TI part
> >=20
> > Hi B,
> >=20
> > Thanks for the Data Manual on the TI part, but I really need to know
> > how it is configured for use in bobcat.  Ala the info in the memory
> > map document, except for the TI part.  What IRQs should be used for
> > what sockets and memory assignments and so forth.
> >=20
> > Cheers,
> >=20
> > a
