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Subject: RE: assignments & settings for TI part
Date: Mon, 7 May 2007 18:19:41 -0700
Message-ID: <BB375AF679D4A34E9CA8DFA650E2B04E03994A40@onstor-exch02.onstor.net>
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Thread-Topic: assignments & settings for TI part
Thread-Index: AceRBItp/U12d7VNT6GFRXc1/riqDwAAwv6RAAGaI1A=
From: "Warren Gale" <warren.gale@onstor.com>
To: "Brian Stark" <brian.stark@onstor.com>,
	"Andy Sharp" <andy.sharp@onstor.com>

Andy,
  Dan did some changes that are in BSD drivers for the TI Part.
If I remember right we look at the ID and do some different stuff
depending on which part is there...


There was something in an e-mail thread about interrupts.
 > Dan, the TI controller can only map socket A interrupts to INTA_L and

 > socket B interrupts to INTB_L.  This is basically reversed from the=20
 > old Bobcat since we program the Intel controller to generate socket A

 > interrupts on PCI INTB_L / PMC INT8_L and socket B interrupts on PCI=20
 > INTA_L / PMC INT9_L.  On the new board, we have to reverse the=20
 > interrupts inside the PMC.  Can you build a BSD image that looks for=20
 > socket A interrupts on PCI INTA_L / PMC INT9_L (IM11) and socket B=20
 > interrupts on PCI INTB_L / PMC INT8_L (IM10)?
 >

Here is the change list numbers and the files Dan modified to=20
get it to work with BSD.


Change List #'s  21194, 21246

Files:
//depot/R1_3_3_work/openbsd/src/sys/arch/pmonmips/pci/pcic_pci_machdep.c
#4 edit
//depot/R1_3_3_work/openbsd/src/sys/arch/pmonmips/pmonmips/kgdb_machdep.
c#4 edit
//depot/R1_3_3_work/openbsd/src/sys/arch/pmonmips/pmonmips/machdep.c#4
edit
//depot/R1_3_3_work/openbsd/src/sys/dev/ic/i82365.c#4 edit
//depot/R1_3_3_work/openbsd/src/sys/dev/pci/i82365_pci.c#4 edit
//depot/R1_3_3_work/openbsd/src/sys/dev/pci/pci.c#4 edit
//depot/R1_3_3_work/openbsd/src/sys/dev/pci/pcidevs.h#4 edit
//depot/R1_3_3_work/openbsd/src/sys/dev/pci/pcidevs_data.h#4 edit

Hope this helps :)
Warren

-----Original Message-----
From: Brian Stark=20
Sent: Monday, May 07, 2007 5:27 PM
To: Andy Sharp
Cc: Warren Gale
Subject: Re: assignments & settings for TI part

Andy,

The mem map and interrupts are configured in prom and are set up
identically to the Intel part.  Let me dig through some old emails to
see if Dan did anything differently in bsd.  If not, then prom will
serve as the best example, and Warren can help answer questions.


Brian



-----Original Message-----
From: Andy Sharp
To: Brian Stark
Sent: Mon May 07 17:05:10 2007
Subject: assignments & settings for TI part

Hi B,

Thanks for the Data Manual on the TI part, but I really need to know
how it is configured for use in bobcat.  Ala the info in the memory map
document, except for the TI part.  What IRQs should be used for what
sockets and memory assignments and so forth.

Cheers,

a
