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Subject: RE: Standalone SSC processor
Date: Wed, 3 Jan 2007 20:17:47 -0800
Message-ID: <7FAAF80773AE7D4CB35AA7A8CC8D49D73EF6CEF8@onstor-exch02.onstor.net>
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Thread-Topic: Standalone SSC processor
thread-index: AccvcC8MKPhAFpoySeqFO2CXyoqSOwAAG4uA
From: "Brian Stark" <brian.stark@onstor.com>
To: "Andy Sharp" <andy.sharp@onstor.com>,
	"dl-Cougar" <dl-Cougar@onstor.com>

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Andy,

A couple of things to consider with your proposal:

- If the Qlogic chip that supports PCI-X is used instead of the PCI-e =
version, the connection between the 1125 and 1480s is problematic.  My =
plan was to use 32-bit PCI as defined today in the block diagram, but =
this means the 1480 PCI bus has to run at 33MHz due to the TI CF =
controller.  This wouldn't be enough bandwidth for the FC controllers =
even in the native 4 port config and especially the additional 4 FC port =
expansion case.  We could put a PCI-PCI bridge down like we do on Bobcat =
to run PCI busses at different frequencies, but this would take up about =
as much space as the HT21000 Southbridge.

- Speaking of bandwidth, we'll be pushing the limits of the 64-bit, =
133MHz PCI-X bus with multiple FC ports.  With 4 lanes of PCI-e to each =
Qlogic dual-port controller, that's a theoretical throughput of 10Gbps =
full-duplex for 2 FC ports.  However, the PCI-X bus would have to handle =
up to 8 FC ports with the expansion case.

- The PCI-X spec specifies that only point-to-point connections are made =
when running 133MHz.  Even though we could probably do more since the =
design is embedded, the expansion case that adds 2 more Qlogics =
definitely doesn't work.  We would then have to add bridge chips for =
electrical isolation, and these have essentially the same latency as the =
current HT21000.  The good news about PCI-e is that the lanes are =
electrically isolated already.


Brian


> -----Original Message-----
> From: Andrew Sharp [mailto:andy.sharp@onstor.com]
> Sent: Wednesday, January 03, 2007 11:49 AM
> To: Brian Stark; dl-Cougar
> Subject: Re: Standalone SSC processor
>
> On Wed, 3 Jan 2007 09:57:25 -0800 "Brian Stark"
> <brian.stark@onstor.com> wrote:
>
> > Hi,
> >
> > Just an update on the discussion that we had yesterday in
> the Cougar
> > meeting.  Broadcom has the SiByte 1125H processor that provides the
> > following:
> >
> > - 1 CPU core
> > - 32-bit PCI bus
> > - 2 * GE interfaces
> > - DDR memory controller
> > - 2 UARTs
> >
> > I am going to look at using the 1125 as a standalone
> processor, and as
> > we discussed yesterday, this will largely be a function of
> board space
> > and cost.  If we move forward with the 1125, then I would propose
> > eliminating the BCM5715 dual MAC and using the native GE
> interfaces of
> > the 1125.  I would also look at using soldered-down DDR1
> SDRAM that is
> > fixed at 512MB if that helps with the layout.
>
> While we are getting rid of the separate dual gigE chip, we
> could also get rid of the separate south bridge chip and run
> the PCI-X bus of the 1480s at 64 bits/133MHz, and put the
> Qlogic controllers directly on that bus.  The 32 bit PCI bus
> on the 1125 can handle the CF controller at that point.  The
> Qlogics could DMA directly into the 1480s memory without the
> latency of going through another bus/bottleneck, as well as
> eliminating the notion that the FPs are best run on the second node.
>
> Cheers,
>
> a
>=20


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<P><FONT size=3D2>Andy,<BR><BR>A couple of things to consider with your =
proposal:<BR><BR>- If the Qlogic chip that supports PCI-X is used =
instead of the PCI-e version, the connection between the 1125 and 1480s =
is problematic.&nbsp; My plan was to use 32-bit PCI as defined today in =
the block diagram, but this means the 1480 PCI bus has to run at 33MHz =
due to the TI CF controller.&nbsp; This wouldn't be enough bandwidth for =
the FC controllers even in the native 4 port config and especially the =
additional 4 FC port expansion case.&nbsp; We could put a PCI-PCI bridge =
down like we do on Bobcat to run PCI busses at different frequencies, =
but this would take up about as much space as the HT21000 =
Southbridge.<BR><BR>- Speaking of bandwidth, we'll be pushing the limits =
of the 64-bit, 133MHz PCI-X bus with multiple FC ports.&nbsp; With 4 =
lanes of PCI-e to each Qlogic dual-port controller, that's a theoretical =
throughput of 10Gbps full-duplex for 2 FC ports.&nbsp; However, the =
PCI-X bus would have to handle up to 8 FC ports with the expansion =
case.<BR><BR>- The PCI-X spec specifies that only point-to-point =
connections are made when running 133MHz.&nbsp; Even though we could =
probably do more since the design is embedded, the expansion case that =
adds 2 more Qlogics definitely doesn't work.&nbsp; We would then have to =
add bridge chips for electrical isolation, and these have essentially =
the same latency as the current HT21000.&nbsp; The good news about PCI-e =
is that the lanes are electrically isolated =
already.<BR><BR><BR>Brian<BR><BR><BR>&gt; -----Original =
Message-----<BR>&gt; From: Andrew Sharp [<A =
href=3D"mailto:andy.sharp@onstor.com">mailto:andy.sharp@onstor.com</A>]<B=
R>&gt; Sent: Wednesday, January 03, 2007 11:49 AM<BR>&gt; To: Brian =
Stark; dl-Cougar<BR>&gt; Subject: Re: Standalone SSC =
processor<BR>&gt;<BR>&gt; On Wed, 3 Jan 2007 09:57:25 -0800 "Brian =
Stark"<BR>&gt; &lt;brian.stark@onstor.com&gt; wrote:<BR>&gt;<BR>&gt; =
&gt; Hi,<BR>&gt; &gt;<BR>&gt; &gt; Just an update on the discussion that =
we had yesterday in<BR>&gt; the Cougar<BR>&gt; &gt; meeting.&nbsp; =
Broadcom has the SiByte 1125H processor that provides the<BR>&gt; &gt; =
following:<BR>&gt; &gt;<BR>&gt; &gt; - 1 CPU core<BR>&gt; &gt; - 32-bit =
PCI bus<BR>&gt; &gt; - 2 * GE interfaces<BR>&gt; &gt; - DDR memory =
controller<BR>&gt; &gt; - 2 UARTs<BR>&gt; &gt;<BR>&gt; &gt; I am going =
to look at using the 1125 as a standalone<BR>&gt; processor, and =
as<BR>&gt; &gt; we discussed yesterday, this will largely be a function =
of<BR>&gt; board space<BR>&gt; &gt; and cost.&nbsp; If we move forward =
with the 1125, then I would propose<BR>&gt; &gt; eliminating the BCM5715 =
dual MAC and using the native GE<BR>&gt; interfaces of<BR>&gt; &gt; the =
1125.&nbsp; I would also look at using soldered-down DDR1<BR>&gt; SDRAM =
that is<BR>&gt; &gt; fixed at 512MB if that helps with the =
layout.<BR>&gt;<BR>&gt; While we are getting rid of the separate dual =
gigE chip, we<BR>&gt; could also get rid of the separate south bridge =
chip and run<BR>&gt; the PCI-X bus of the 1480s at 64 bits/133MHz, and =
put the<BR>&gt; Qlogic controllers directly on that bus.&nbsp; The 32 =
bit PCI bus<BR>&gt; on the 1125 can handle the CF controller at that =
point.&nbsp; The<BR>&gt; Qlogics could DMA directly into the 1480s =
memory without the<BR>&gt; latency of going through another =
bus/bottleneck, as well as<BR>&gt; eliminating the notion that the FPs =
are best run on the second node.<BR>&gt;<BR>&gt; Cheers,<BR>&gt;<BR>&gt; =
a<BR>&gt; </FONT></P></BODY></HTML>
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