X-MimeOLE: Produced By Microsoft Exchange V6.5
Received: by onstor-exch02.onstor.net 
	id <01C72556.5471F106@onstor-exch02.onstor.net>; Thu, 21 Dec 2006 15:18:31 -0800
MIME-Version: 1.0
Content-Type: multipart/alternative;
	boundary="----_=_NextPart_001_01C72556.5471F106"
Content-class: urn:content-classes:message
Subject: Cougar meeting minutes
Date: Thu, 21 Dec 2006 15:18:31 -0800
Message-ID: <BB375AF679D4A34E9CA8DFA650E2B04E01D4CC46@onstor-exch02.onstor.net>
X-MS-Has-Attach: 
X-MS-TNEF-Correlator: 
Thread-Topic: Cougar meeting minutes
thread-index: AcclVlR7vaqsmxlZQV6XYh5XdzIKLw==
From: "Tim Gardner" <tim.gardner@onstor.com>
To: "dl-Cougar" <dl-Cougar@onstor.com>

This is a multi-part message in MIME format.

------_=_NextPart_001_01C72556.5471F106
Content-Type: text/plain;
	charset="us-ascii"
Content-Transfer-Encoding: quoted-printable

This note summarizes a couple of Cougar meetings that were held this
past week.

*	The Cougar requirements state that the initial product release
must support 60K NFS ops and 500MB/s streaming read performance.
The issue with this is that the initial HW will only support 4 gige
interfaces and the initial SW will not support the expansion card that
provides 4 additional gige interfaces.
I discussed this with Narayan. He said it is acceptable for the first
product release to only support 4 gige interfaces and that this product
does not need to do 500MB/s.
This is ok so long as we can support a follow on product 3 months or so
later that is capable of 500MB/s. The 500MB/s implies that it must
support more than 4 gige interfaces.
*	During a SW architecture discussion we outlined a plan for an
architecture that will be capable of meeting the performance
requirements:
On the node to which the gige interface is connected we will run: ACPU0,
NCPU0, FP0 and FP1. The FP cores will also run FC functionality.
On the other node we will run ACPU1, FP2, SSC and either NCPU1 or FP3
depending on whether or not the gige expansion board is installed.
*	The following questions came out of this discussion:
o	Could the HW layout be setup so that in the base configuration 2
gige interfaces are wired to each 1480? The expansion would then connect
an
additional 2 interfaces to each 1480. Brian needs to respond to this.
o	We need to verify that the Qlogic can DMA from either bank of
memory. Brian?
o	Why is the BCM5715 attached to the PCI-e and not the PCI-x?
Brian?

*	The proposed architecture means that we have to solve the
following SW problems:
o	The ACPU functionality will not need to be made SMP if we tie
all operations to a specific volume to an ACPU.
But we will need to handle some locking on the data structures (mostly
VS related) that are shared by volumes.
o	We discussed how to perform load balancing. An idea was proposed
to add an ACPU triage queue that would be
at the highest processing priority. Incoming packets placed on this
queue would need to be triaged to determine which
ACPU should be used to process the packet. The packet would be moved to
the appropriate ACPU pending queue as
part of triage.
o	We have not yet discussed what it means to split FC
functionality between multiple nodes.

*	Cougar planning continues. Currently thinking about doing the
linux port to bobcat early in the project.=20
o	Much of the early development env work is common to cougar and
the bobcat port.
o	Doing the bobcat port early will provide a platform for doing
SSC app porting. This will enable more developers to start the
porting earlier and to work in parallel as there are plenty of bobcats
available and there will be very few cougars.
o	There is likely to be slack in the schedule while waiting for
cougar HW. This could be utilized to bring up linux on the
bobcat R9000.


------_=_NextPart_001_01C72556.5471F106
Content-Type: text/html;
	charset="us-ascii"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
6.5.7650.28">
<TITLE>Cougar meeting minutes</TITLE>
</HEAD>
<BODY>
<!-- Converted from text/rtf format -->

<P ALIGN=3DLEFT><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">This =
note summarizes a couple of Cougar meetings that were held this past =
week.</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"></SPAN></P>

<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Symbol">&#183;<FONT =
FACE=3D"Courier =
New">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT></FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> =
<FONT SIZE=3D2 FACE=3D"Arial">The Cougar requirements state that =
the</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT =
SIZE=3D2 FACE=3D"Arial">initial</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Arial"></FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"> <FONT SIZE=3D2 FACE=3D"Arial">product release must =
support 60K NFS ops and 500MB/s streaming read performance.<BR>
The issue with this is that the initial HW will only support =
4</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT =
SIZE=3D2 FACE=3D"Arial">gige interfaces and the initial SW will not =
support the expansion card that provides 4 additional gige =
interfaces.<BR>
I discussed this with Narayan. He said it is acceptable for the first =
product release to only support 4 gige interfaces and that this product =
does not need to do 500MB/s.<BR>
This is ok so long as we can support a follow on product 3 months or so =
later that is capable of 500MB/s. The 500MB/s implies that it must =
support more than 4 gige interfaces</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Arial">.</FONT></SPAN></P>

<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Symbol">&#183;<FONT =
FACE=3D"Courier New">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT></FONT> =
<FONT SIZE=3D2 FACE=3D"Arial">During a SW architecture discussion we =
outlined a plan for an architecture that will be capable of meeting =
the</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT =
SIZE=3D2 FACE=3D"Arial">performance requirements:<BR>
On the node to which the gige interface is connected we will run: ACPU0, =
NCPU0,</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial"> FP0 and FP1. The FP cores =
will also run FC functionality.<BR>
On the other node we will run ACPU1, FP2, SSC and either NCPU1 or FP3 =
depending on whether or not the gige</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">expansion</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial"></FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">board is installed.</FONT></SPAN></P>

<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Symbol">&#183;<FONT =
FACE=3D"Courier New">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT></FONT> =
<FONT SIZE=3D2 FACE=3D"Arial">The following questions came out of this =
discussion:</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Courier =
New">o&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">Could the HW layout be setup so that in the base =
configuration 2 gige interface</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Arial">s</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial"></FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">are</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial"> wired to each =
1480</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"><FONT =
SIZE=3D2 FACE=3D"Arial">?</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial"> The expansion would then =
connect an<BR>
additional 2 interfaces to each 1480.</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Arial"> Brian needs to respond to this.</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Courier =
New">o&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">We need to verify that the Qlogic can DMA from either =
bank of memory.</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial"> Brian?</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Courier =
New">o&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT> <FONT SIZE=3D2 =
FACE=3D"Arial">Why is the BCM5715 attached to the PCI-e and not the =
PCI-x?</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial"> Brian?</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"></SPAN>
</P>

<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Symbol">&#183;<FONT =
FACE=3D"Courier =
New">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT></FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">The proposed architecture</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Arial"> means that we have to solve the following SW =
problems:</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Courier =
New">o&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">The ACPU functionality will not need to be made SMP if we =
tie all operations to a specific volume to an ACPU.<BR>
But we will need to handle some locking on the data structures (mostly =
VS related) that are shared by volumes.</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Courier =
New">o&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT> <FONT SIZE=3D2 =
FACE=3D"Arial">We discussed how to perform load balancing. An idea was =
proposed to add an ACPU triage queue that would be<BR>
</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"><FONT =
SIZE=3D2 FACE=3D"Arial">at</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">the highest</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">processing priority. Incoming packets placed on this =
queue would need to be triaged to determine which<BR>
ACPU should be used to process the packet. The packet would be moved to =
the appropriate</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"> <FONT SIZE=3D2 FACE=3D"Arial">ACPU</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">pending qu</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">eue as<BR>
part of triage.</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Courier =
New">o&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">We have not yet</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">discussed what it means to split FC functionality between =
multiple nodes.</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"></SPAN>
</P>

<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Symbol">&#183;<FONT =
FACE=3D"Courier =
New">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT></FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">Cougar planning continues. Currently thinking about doing =
the linux port to bobcat early in the project.</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> </SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Courier =
New">o&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">Much of the early development env work is common to =
cougar and the bobcat port.</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Courier =
New">o&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> <FONT SIZE=3D2 =
FACE=3D"Arial">Doing the bobcat port early will provide a platform for =
doing SSC app porting</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">. This will enable more =
developers to start the<BR>
porting earlier and to work in parallel as there are plenty of bobcats =
available and there will be very few cougars.</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Courier =
New">o&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT> <FONT SIZE=3D2 =
FACE=3D"Arial">There is likely to be slack in the schedule while waiting =
for cougar HW. This could be utilized to bring up linux on the<BR>
bobcat R9000.<BR>
</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"></SPAN>
</P>

</BODY>
</HTML>
------_=_NextPart_001_01C72556.5471F106--
