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Subject: RE: A picture is worth a thousand words...
Date: Thu, 13 Dec 2007 12:06:30 -0800
Message-ID: <BB375AF679D4A34E9CA8DFA650E2B04E0714F566@onstor-exch02.onstor.net>
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Thread-Topic: A picture is worth a thousand words...
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References: <BB375AF679D4A34E9CA8DFA650E2B04E0714F424@onstor-exch02.onstor.net>
From: "Bob Miller" <bob.miller@onstor.com>
To: "Brian Stark" <brian.stark@onstor.com>,
	"dl-Cougar" <dl-Cougar@onstor.com>
Cc: "Paul Negus" <paul.negus@onstor.com>,
	"Tom Gallivan" <tom.gallivan@onstor.com>

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Brian and Pat
As you said this shows it all! Great piece of work!
B

_____________________________________________
From: Brian Stark=20
Sent: Thursday, December 13, 2007 10:41 AM
To: dl-Cougar
Cc: Bob Miller; Paul Negus; Tom Gallivan
Subject: A picture is worth a thousand words...


As discussed in the Cougar dev meeting on Tuesday, we believe the
problem with the TXRX MC1 DIMMs on the Rev 2 motherboards is related to
switching noise on the 12V power plane.  Well, the following pictures
show all that we need to know in terms of why Rev 1 worked and Rev 2
doesn't.  Take a look at the following attachments:

PJH_V12_switching.bmp -- this is a measurement of the 12V plane near one
of the low-voltage power circuits on the Rev 2 motherboard.  Notice the
~1.5V peak-to-peak noise that happens at a frequency of ~900MHz.

PJH_d19.dmp --- this is bit 19 in MC1 that consistently fails during
memory test.  Again, notice the ~500mW peak-to-peak noise that happens
at a frequency of 900MHz.  This noise is being coupled from the 12V
plane that sits directly above the layer that bit 19 is routed in.
Given that DDR2 operates with a center line voltage of 900mV, 500mV of
noise can easily flip a bit from 1 to 0 or vice versa and cause memory
failures.

PJH_V12_oki.bmp -- same 12V capture as the above on the Rev 1 Oki fabs.
Although there's still noise on the 12V, the amplitude is greatly
reduced.

PJH_d19_oki.bmp -- bit 19 capture on the Rev 1 Oki fabs.  There's still
some pertubation caused by the 12V plane, but the amplitude is not
enough to cause memory corruption.  This is why Rev 1 is working and Rev
2 is not.


We have some theories on why there is such a difference between the Rev
1 and Rev 2 fabs, but we'll probably never know the exact cause(s).  The
important thing is to clean up the 12V switching noise and isolate the
memory circuits from any noise on this plane, which is what we'll be
addressing in the next rev of the motherboard.

Special thanks to Pat Haverty for taking these captures and helping to
isolate the problem.


Brian


 << File: PJH_V12_switching.bmp >>  << File: PJH_d19.bmp >>  << File:
PJH_V12_oki.bmp >>  << File: PJH_d19_oki.bmp >>=20





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<TITLE>RE: A picture is worth a thousand words...</TITLE>
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<!-- Converted from text/rtf format -->

<P DIR=3DLTR><SPAN LANG=3D"en-us"><FONT COLOR=3D"#1F497D" =
FACE=3D"Calibri">Brian and Pat</FONT></SPAN></P>

<P DIR=3DLTR><SPAN LANG=3D"en-us"><FONT COLOR=3D"#1F497D" =
FACE=3D"Calibri">As you said this shows it all! Great piece of =
work</FONT></SPAN><SPAN LANG=3D"en-us"><FONT COLOR=3D"#1F497D" =
FACE=3D"Calibri">!</FONT></SPAN></P>

<P DIR=3DLTR><SPAN LANG=3D"en-us"><FONT COLOR=3D"#1F497D" =
FACE=3D"Calibri">B</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN></P>

<P DIR=3DLTR><SPAN LANG=3D"en-us"></SPAN></P>

<P DIR=3DLTR><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Tahoma">_____________________________________________<BR>
</FONT></SPAN><SPAN LANG=3D"en-us"><B></B></SPAN><SPAN =
LANG=3D"en-us"><B></B></SPAN><SPAN LANG=3D"en-us"><B><FONT SIZE=3D2 =
FACE=3D"Tahoma">From:</FONT></B></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Tahoma"> Brian Stark<BR>
</FONT></SPAN><SPAN LANG=3D"en-us"><B></B></SPAN><SPAN =
LANG=3D"en-us"><B></B></SPAN><SPAN LANG=3D"en-us"><B><FONT SIZE=3D2 =
FACE=3D"Tahoma">Sent:</FONT></B></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Tahoma"> Thursday, December 13, 2007 10:41 AM<BR>
</FONT></SPAN><SPAN LANG=3D"en-us"><B></B></SPAN><SPAN =
LANG=3D"en-us"><B></B></SPAN><SPAN LANG=3D"en-us"><B><FONT SIZE=3D2 =
FACE=3D"Tahoma">To:</FONT></B></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Tahoma"> dl-Cougar<BR>
</FONT></SPAN><SPAN LANG=3D"en-us"><B></B></SPAN><SPAN =
LANG=3D"en-us"><B></B></SPAN><SPAN LANG=3D"en-us"><B><FONT SIZE=3D2 =
FACE=3D"Tahoma">Cc:</FONT></B></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Tahoma"> Bob Miller; Paul Negus; Tom Gallivan<BR>
</FONT></SPAN><SPAN LANG=3D"en-us"><B></B></SPAN><SPAN =
LANG=3D"en-us"><B></B></SPAN><SPAN LANG=3D"en-us"><B><FONT SIZE=3D2 =
FACE=3D"Tahoma">Subject:</FONT></B></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Tahoma"> A picture is worth a =
thousand words...</FONT></SPAN></P>

<P DIR=3DLTR><SPAN LANG=3D"en-us"></SPAN></P>

<P DIR=3DLTR><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Arial">As discussed in the Cougar dev meeting on Tuesday, we =
believe the problem with the TXRX MC1 DIMMs on the Rev 2 motherboards is =
related to switching noise on the 12V power plane.&nbsp; Well, the =
following pictures show all that we need to know in terms of why Rev 1 =
worked and Rev 2 doesn't.&nbsp; Take a look at the following =
attachments:</FONT></SPAN></P>

<P DIR=3DLTR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Arial">PJH_V12_switching.bmp -- this is a measurement of the 12V =
plane near one of the low-voltage power circuits on the Rev 2 =
motherboard.&nbsp; Notice the ~1.5V peak-to-peak noise that happens at a =
frequency of ~900MHz.</FONT></SPAN></P>

<P DIR=3DLTR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Arial">PJH_d19.dmp --- this is bit 19 in MC1 that consistently =
fails during memory test.&nbsp; Again, notice the ~500mW peak-to-peak =
noise that happens at a frequency of 900MHz.&nbsp; This noise is being =
coupled from the 12V plane that sits directly above the layer that bit =
19 is routed in.&nbsp; Given that DDR2 operates with a center line =
voltage of 900mV, 500mV of noise can easily flip a bit from 1 to 0 or =
vice versa and cause memory failures.</FONT></SPAN></P>

<P DIR=3DLTR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Arial">PJH_V12_oki.bmp -- same 12V capture as the above on the =
Rev 1 Oki fabs.&nbsp; Although there's still noise on the 12V, the =
amplitude is greatly reduced.</FONT></SPAN></P>

<P DIR=3DLTR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Arial">PJH_d19_oki.bmp -- bit 19 capture on the Rev 1 Oki =
fabs.&nbsp; There's still some pertubation caused by the 12V plane, but =
the amplitude is not enough to cause memory corruption.&nbsp; This is =
why Rev 1 is working and Rev 2 is not.</FONT></SPAN></P>
<BR>

<P DIR=3DLTR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">We have =
some theories on why there is such a difference between the Rev 1 and =
Rev 2 fabs, but we'll probably never know the exact cause(s).&nbsp; The =
important thing is to clean up the 12V switching noise and isolate the =
memory circuits from any noise on this plane, which is what we'll be =
addressing in the next rev of the motherboard.</FONT></SPAN></P>

<P DIR=3DLTR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">Special =
thanks to Pat Haverty for taking these captures and helping to isolate =
the problem.</FONT></SPAN></P>
<BR>

<P DIR=3DLTR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Arial">Brian</FONT></SPAN></P>
<BR>

<P DIR=3DLTR><SPAN LANG=3D"en-us"><FONT FACE=3D"Calibri">&nbsp;&lt;&lt; =
File: PJH_V12_switching.bmp &gt;&gt;&nbsp; &lt;&lt; File: PJH_d19.bmp =
&gt;&gt;&nbsp; &lt;&lt; File: PJH_V12_oki.bmp &gt;&gt;&nbsp; &lt;&lt; =
File: PJH_d19_oki.bmp &gt;&gt;</FONT></SPAN><SPAN =
LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN LANG=3D"en-us"> =
</SPAN></P>
<BR>
<BR>

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