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Subject: RE: BMFPGA address clarification
Date: Sun, 11 Nov 2007 08:42:28 -0800
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Thread-Topic: BMFPGA address clarification
Thread-Index: AcgjRHy1nd0kEsicRJ6cKt8NU4E+gABPVxBX
From: "Brian Stark" <brian.stark@onstor.com>
To: "Andy Sharp" <andy.sharp@onstor.com>
Cc: "Maxim Kozlovsky" <maxim.kozlovsky@onstor.com>

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Andy,
=20
For the physical address, it depends on the perspective.  From the =
BM-FPGA, the address is 32-bit and is 0x1f40.0000.  From the 1125, the =
address is 40-bit and is 0xf8.1f40.0000.  The 'f8' directs the internal =
access to the PCI bus, which is then stripped before going out on PCI, =
and the resulting PCI address is 0x1f40.0000.
=20
This 40-bit address is not mapped into kseg1, although the PROM has set =
up a TLB entry at 0x5000.0000 to access all BM-FPGA registers.  Lastly, =
the BM-FPGA is the only FPGA on Cougar.
=20
=20
Brian
=20

________________________________

From: Andy Sharp
Sent: Fri 11/9/2007 6:50 PM
To: Brian Stark
Cc: Maxim Kozlovsky
Subject: BMFPGA address clarification



Howdy pards,

So, I'm holding a doc that Brian sent a little while ago that lists the
BMFPGA at phys 0x1f40.0000, but Max showed me a document that listed
the address as 0xf8.1f40.0000, ie., indicating that it was in the PCI
bus address space.  I know that some FPGA is visible on the PCI bus
scan, but I guess in my mind it was not the BMFPGA.

Which is it?  Or is it a little from column A and a little from column
B?  Is that chunklet of PCI space mapped into the KSEG1 space some way?
It makes a big difference to how much code we have to change to get the
chassisd working on cougar.

Cheers,

a



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<HTML dir=3Dltr><HEAD><TITLE>BMFPGA address clarification</TITLE>=0A=
<META http-equiv=3DContent-Type content=3D"text/html; charset=3Dunicode">=0A=
<META content=3D"MSHTML 6.00.2900.3199" name=3DGENERATOR></HEAD>=0A=
<BODY>=0A=
<DIV id=3DidOWAReplyText92403 dir=3Dltr>=0A=
<DIV dir=3Dltr><FONT face=3DArial color=3D#000000 =
size=3D2>Andy,</FONT></DIV>=0A=
<DIV dir=3Dltr><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>=0A=
<DIV dir=3Dltr><FONT face=3DArial size=3D2>For the physical address, it =
depends on the perspective.&nbsp; From the BM-FPGA, the address is =
32-bit and is 0x1f40.0000.&nbsp; From the 1125, the address is 40-bit =
and is 0xf8.1f40.0000.&nbsp; The 'f8' directs the internal access to the =
PCI bus, which is then stripped before going out on PCI, and the =
resulting PCI address is 0x1f40.0000.</FONT></DIV>=0A=
<DIV dir=3Dltr><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>=0A=
<DIV dir=3Dltr><FONT face=3DArial size=3D2>This 40-bit address is not =
mapped into kseg1, although the PROM has set up a TLB entry at =
0x5000.0000 to access all BM-FPGA registers.&nbsp; Lastly, the BM-FPGA =
is the only FPGA on Cougar.</FONT></DIV>=0A=
<DIV dir=3Dltr><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>=0A=
<DIV dir=3Dltr><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>=0A=
<DIV dir=3Dltr><FONT face=3DArial size=3D2>Brian</FONT></DIV>=0A=
<DIV dir=3Dltr><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV></DIV>=0A=
<DIV dir=3Dltr><BR>=0A=
<HR tabIndex=3D-1>=0A=
<FONT face=3DTahoma size=3D2><B>From:</B> Andy Sharp<BR><B>Sent:</B> Fri =
11/9/2007 6:50 PM<BR><B>To:</B> Brian Stark<BR><B>Cc:</B> Maxim =
Kozlovsky<BR><B>Subject:</B> BMFPGA address =
clarification<BR></FONT><BR></DIV>=0A=
<DIV>=0A=
<P><FONT size=3D2>Howdy pards,<BR><BR>So, I'm holding a doc that Brian =
sent a little while ago that lists the<BR>BMFPGA at phys 0x1f40.0000, =
but Max showed me a document that listed<BR>the address as =
0xf8.1f40.0000, ie., indicating that it was in the PCI<BR>bus address =
space.&nbsp; I know that some FPGA is visible on the PCI bus<BR>scan, =
but I guess in my mind it was not the BMFPGA.<BR><BR>Which is it?&nbsp; =
Or is it a little from column A and a little from column<BR>B?&nbsp; Is =
that chunklet of PCI space mapped into the KSEG1 space some way?<BR>It =
makes a big difference to how much code we have to change to get =
the<BR>chassisd working on =
cougar.<BR><BR>Cheers,<BR><BR>a<BR></FONT></P></DIV></BODY></HTML>
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