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From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Subject: [PATCH] IP22: Fix crashes due to wrong L1_CACHE_BYTES
To: linux-mips@linux-mips.org
cc: ralf@linux-mips.org
Message-Id: <20080627215226.D1B5EE2F71@solo.franken.de>
Date: 	Fri, 27 Jun 2008 23:52:26 +0200 (CEST)
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X-OriginalArrivalTime: 27 Jun 2008 21:53:43.0997 (UTC) FILETIME=[44C1AED0:01C8D8A0]

The introduction of a real dma cache invalidate makes it important
to have a correct cache line size, otherwise the kernel will gives
out two memory segment, which might share one cache line. The R4400
Indy/Indigo2 CPU modules are using a second level cache line size
of 128 bytes, so MIPS_L1_CACHE_SHIFT needs to be bumped up to 7 for
IP22.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e5a7c5d..24c5dee 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1006,7 +1006,7 @@ config BOOT_ELF32
 config MIPS_L1_CACHE_SHIFT
 	int
 	default "4" if MACH_DECSTATION
-	default "7" if SGI_IP27 || SGI_IP28 || SNI_RM
+	default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
 	default "4" if PMC_MSP4200_EVAL
 	default "5"
 

