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From: Manuel Lauss <mano@roarinelk.homelinux.net>
To: Linux-MIPS <linux-mips@linux-mips.org>
CC: Manuel Lauss <mano@roarinelk.homelinux.net>
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Date: Sun, 21 Dec 2008 00:26:18 -0800
Subject: [PATCH 05/14] Alchemy: pb1200: update CPLD cascade irq handler.
Thread-Topic: [PATCH 05/14] Alchemy: pb1200: update CPLD cascade irq handler.
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Tested on Db1200.

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
---
 arch/mips/alchemy/devboards/pb1200/irqmap.c |   87 +++++++++--------------=
---
 1 files changed, 30 insertions(+), 57 deletions(-)

diff --git a/arch/mips/alchemy/devboards/pb1200/irqmap.c b/arch/mips/alchem=
y/devboards/pb1200/irqmap.c
index 1f92fec..fe47498 100644
--- a/arch/mips/alchemy/devboards/pb1200/irqmap.c
+++ b/arch/mips/alchemy/devboards/pb1200/irqmap.c
@@ -47,77 +47,50 @@ struct au1xxx_irqmap __initdata au1xxx_irq_map[] =3D {
 /*
  * Support for External interrupts on the Pb1200 Development platform.
  */
-static volatile int pb1200_cascade_en;
=20
-irqreturn_t pb1200_cascade_handler(int irq, void *dev_id)
+static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *d)
 {
 	unsigned short bisr =3D bcsr->int_status;
-	int extirq_nr =3D 0;
-
-	/* Clear all the edge interrupts. This has no effect on level. */
-	bcsr->int_status =3D bisr;
-	for ( ; bisr; bisr &=3D bisr - 1) {
-		extirq_nr =3D PB1200_INT_BEGIN + __ffs(bisr);
-		/* Ack and dispatch IRQ */
-		do_IRQ(extirq_nr);
-	}
-
-	return IRQ_RETVAL(1);
-}
=20
-inline void pb1200_enable_irq(unsigned int irq_nr)
-{
-	bcsr->intset_mask =3D 1 << (irq_nr - PB1200_INT_BEGIN);
-	bcsr->intset =3D 1 << (irq_nr - PB1200_INT_BEGIN);
+	for ( ; bisr; bisr &=3D bisr - 1)
+		generic_handle_irq(PB1200_INT_BEGIN + __ffs(bisr));
 }
=20
-inline void pb1200_disable_irq(unsigned int irq_nr)
+/* NOTE: both the enable and mask bits must be cleared, otherwise the
+ * CPLD generates tons of spurious interrupts (at least on the DB1200).
+ */
+static void pb1200_mask_irq(unsigned int irq_nr)
 {
 	bcsr->intclr_mask =3D 1 << (irq_nr - PB1200_INT_BEGIN);
 	bcsr->intclr =3D 1 << (irq_nr - PB1200_INT_BEGIN);
+	au_sync();
 }
=20
-static unsigned int pb1200_setup_cascade(void)
-{
-	return request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
-			   0, "Pb1200 Cascade", &pb1200_cascade_handler);
-}
-
-static unsigned int pb1200_startup_irq(unsigned int irq)
+static void pb1200_maskack_irq(unsigned int irq_nr)
 {
-	if (++pb1200_cascade_en =3D=3D 1) {
-		int res;
-
-		res =3D pb1200_setup_cascade();
-		if (res)
-			return res;
-	}
-
-	pb1200_enable_irq(irq);
-
-	return 0;
+	bcsr->intclr_mask =3D 1 << (irq_nr - PB1200_INT_BEGIN);
+	bcsr->intclr =3D 1 << (irq_nr - PB1200_INT_BEGIN);
+	bcsr->int_status =3D 1 << (irq_nr - PB1200_INT_BEGIN);	/* ack */
+	au_sync();
 }
=20
-static void pb1200_shutdown_irq(unsigned int irq)
+static void pb1200_unmask_irq(unsigned int irq_nr)
 {
-	pb1200_disable_irq(irq);
-	if (--pb1200_cascade_en =3D=3D 0)
-		free_irq(AU1000_GPIO_7, &pb1200_cascade_handler);
+	bcsr->intset =3D 1 << (irq_nr - PB1200_INT_BEGIN);
+	bcsr->intset_mask =3D 1 << (irq_nr - PB1200_INT_BEGIN);
+	au_sync();
 }
=20
-static struct irq_chip external_irq_type =3D {
+static struct irq_chip pb1200_cpld_irq_type =3D {
 #ifdef CONFIG_MIPS_PB1200
 	.name =3D "Pb1200 Ext",
 #endif
 #ifdef CONFIG_MIPS_DB1200
 	.name =3D "Db1200 Ext",
 #endif
-	.startup  =3D pb1200_startup_irq,
-	.shutdown =3D pb1200_shutdown_irq,
-	.ack      =3D pb1200_disable_irq,
-	.mask     =3D pb1200_disable_irq,
-	.mask_ack =3D pb1200_disable_irq,
-	.unmask   =3D pb1200_enable_irq,
+	.mask		=3D pb1200_mask_irq,
+	.mask_ack	=3D pb1200_maskack_irq,
+	.unmask		=3D pb1200_unmask_irq,
 };
=20
 void __init board_init_irq(void)
@@ -147,15 +120,15 @@ void __init board_init_irq(void)
 		panic("Game over.  Your score is 0.");
 	}
 #endif
+	/* mask & disable & ack all */
+	bcsr->intclr_mask =3D 0xffff;
+	bcsr->intclr =3D 0xffff;
+	bcsr->int_status =3D 0xffff;
+	au_sync();
=20
-	for (irq =3D PB1200_INT_BEGIN; irq <=3D PB1200_INT_END; irq++) {
-		set_irq_chip_and_handler(irq, &external_irq_type,
-					 handle_level_irq);
-		pb1200_disable_irq(irq);
-	}
+	for (irq =3D PB1200_INT_BEGIN; irq <=3D PB1200_INT_END; irq++)
+		set_irq_chip_and_handler_name(irq, &pb1200_cpld_irq_type,
+					 handle_level_irq, "level");
=20
-	/*
-	 * GPIO_7 can not be hooked here, so it is hooked upon first
-	 * request of any source attached to the cascade.
-	 */
+	set_irq_chained_handler(AU1000_GPIO_7, pb1200_cascade_handler);
 }
--=20
1.6.0.4


