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From: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
To: "ralf@linux-mips.org" <ralf@linux-mips.org>, "linux-mips@linux-mips.org"
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Date: Sat, 21 Mar 2009 06:04:21 -0700
Subject: [PATCH] MIPS: Mark Eins: Fix cascading interrupt dispatcher
Thread-Topic: [PATCH] MIPS: Mark Eins: Fix cascading interrupt dispatcher
Thread-Index: AcmqJaoenK+GcGtpTiKplyP5lPZxWg==
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* Fix mis-calculated IRQ bitshift on cascading interrupts
* Prevent cascading interrupt bits being processed afterward

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
---
 arch/mips/emma/markeins/irq.c |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index c2583ec..263132d 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -213,8 +213,7 @@ void emma2rh_irq_dispatch(void)
 		    emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
=20
 #ifdef EMMA2RH_SW_CASCADE
-	if (intStatus &
-	    (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
+	if (intStatus & (1UL << EMMA2RH_SW_CASCADE)) {
 		u32 swIntStatus;
 		swIntStatus =3D emma2rh_in32(EMMA2RH_BHIF_SW_INT)
 		    & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
@@ -225,6 +224,8 @@ void emma2rh_irq_dispatch(void)
 			}
 		}
 	}
+	/* Skip S/W interrupt */
+	intStatus &=3D ~(1UL << EMMA2RH_SW_CASCADE);
 #endif
=20
 	for (i =3D 0, bitmask =3D 1; i < 32; i++, bitmask <<=3D 1) {
@@ -238,8 +239,7 @@ void emma2rh_irq_dispatch(void)
 		    emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
=20
 #ifdef EMMA2RH_GPIO_CASCADE
-	if (intStatus &
-	    (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
+	if (intStatus & (1UL << (EMMA2RH_GPIO_CASCADE % 32))) {
 		u32 gpioIntStatus;
 		gpioIntStatus =3D emma2rh_in32(EMMA2RH_GPIO_INT_ST)
 		    & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
@@ -250,6 +250,8 @@ void emma2rh_irq_dispatch(void)
 			}
 		}
 	}
+	/* Skip GPIO interrupt */
+	intStatus &=3D ~(1UL << (EMMA2RH_GPIO_CASCADE % 32));
 #endif
=20
 	for (i =3D 32, bitmask =3D 1; i < 64; i++, bitmask <<=3D 1) {

