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From: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
To: "ralf@linux-mips.org" <ralf@linux-mips.org>, "linux-mips@linux-mips.org"
	<linux-mips@linux-mips.org>
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Date: Sat, 21 Mar 2009 06:06:14 -0700
Subject: [PATCH] MIPS: EMMA2RH: Use handle_edge_irq() handler for GPIO
 interrupts
Thread-Topic: [PATCH] MIPS: EMMA2RH: Use handle_edge_irq() handler for GPIO
 interrupts
Thread-Index: AcmqJeJ7zQ7uBBJ/QSuIhvj1qfe7bw==
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EMMA's GPIO interrupts are latched by GPIO interrupt status register.
In this case, we're encouraged to use handle_edge_irq() handler.

The following changes are made along with replacing set_irq_chip() with
set_irq_chip_and_handler_name(,,handle_edge_irq,"edge"):

* Fix emma2rh_gpio_irq_ack not to disable interrupts

  With handle_edge_irq(), we're not expected to disable interrupts
  when chip->ack is served, so fix it accordingly.  We also add a new
  emma2rh_gpio_irq_mask_ack() for chip->mask_ack operation, instead.

* Remove emma2rh_gpio_irq_end(), as chip->end is no longer served.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
---
 arch/mips/emma/markeins/irq.c |   28 ++++++++++------------------
 1 files changed, 10 insertions(+), 18 deletions(-)

diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 263132d..1e6457c 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -149,37 +149,28 @@ static void emma2rh_gpio_irq_disable(unsigned int irq=
)
=20
 static void emma2rh_gpio_irq_ack(unsigned int irq)
 {
-	u32 reg;
-
 	irq -=3D EMMA2RH_GPIO_IRQ_BASE;
 	emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
-
-	reg =3D emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
-	reg &=3D ~(1 << irq);
-	emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
 }
=20
-static void emma2rh_gpio_irq_end(unsigned int irq)
+static void emma2rh_gpio_irq_mask_ack(unsigned int irq)
 {
 	u32 reg;
=20
-	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
-
-		irq -=3D EMMA2RH_GPIO_IRQ_BASE;
+	irq -=3D EMMA2RH_GPIO_IRQ_BASE;
+	emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
=20
-		reg =3D emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
-		reg |=3D 1 << irq;
-		emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
-	}
+	reg =3D emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
+	reg &=3D ~(1 << irq);
+	emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
 }
=20
 struct irq_chip emma2rh_gpio_irq_controller =3D {
 	.name =3D "emma2rh_gpio_irq",
 	.ack =3D emma2rh_gpio_irq_ack,
 	.mask =3D emma2rh_gpio_irq_disable,
-	.mask_ack =3D emma2rh_gpio_irq_ack,
+	.mask_ack =3D emma2rh_gpio_irq_mask_ack,
 	.unmask =3D emma2rh_gpio_irq_enable,
-	.end =3D emma2rh_gpio_irq_end,
 };
=20
 void emma2rh_gpio_irq_init(void)
@@ -187,8 +178,9 @@ void emma2rh_gpio_irq_init(void)
 	u32 i;
=20
 	for (i =3D 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
-		set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i,
-			     &emma2rh_gpio_irq_controller);
+		set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
+					      &emma2rh_gpio_irq_controller,
+					      handle_edge_irq, "edge");
 }
=20
 static struct irqaction irq_cascade =3D {

