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From: Kevin Cernekee <cernekee@gmail.com>
To: "ralf@linux-mips.org" <ralf@linux-mips.org>
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Date: Thu, 23 Apr 2009 17:36:53 -0700
Subject: [PATCH 3/3] MIPS: Support 64-byte D-cache line size
Thread-Topic: [PATCH 3/3] MIPS: Support 64-byte D-cache line size
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Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
 arch/mips/include/asm/r4kcache.h |    1 +
 arch/mips/mm/c-r4k.c             |   12 ++++++++++++
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kca=
che.h
index 4c140db..387bf59 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -399,6 +399,7 @@ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, =
Hit_Writeback_Inv_SD, 16)
 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,=
 32)
 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_S=
D, 32)
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,=
 64)
 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_S=
D, 64)
 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_S=
D, 128)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 171951d..71fe4cb 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -100,6 +100,12 @@ static inline void r4k_blast_dcache_page_dc32(unsigned=
 long addr)
 	blast_dcache32_page(addr);
 }
=20
+static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
+{
+	R4600_HIT_CACHEOP_WAR_IMPL;
+	blast_dcache64_page(addr);
+}
+
 static void __cpuinit r4k_blast_dcache_page_setup(void)
 {
 	unsigned long  dc_lsize =3D cpu_dcache_line_size();
@@ -110,6 +116,8 @@ static void __cpuinit r4k_blast_dcache_page_setup(void)
 		r4k_blast_dcache_page =3D blast_dcache16_page;
 	else if (dc_lsize =3D=3D 32)
 		r4k_blast_dcache_page =3D r4k_blast_dcache_page_dc32;
+	else if (dc_lsize =3D=3D 64)
+		r4k_blast_dcache_page =3D r4k_blast_dcache_page_dc64;
 }
=20
 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
@@ -124,6 +132,8 @@ static void __cpuinit r4k_blast_dcache_page_indexed_set=
up(void)
 		r4k_blast_dcache_page_indexed =3D blast_dcache16_page_indexed;
 	else if (dc_lsize =3D=3D 32)
 		r4k_blast_dcache_page_indexed =3D blast_dcache32_page_indexed;
+	else if (dc_lsize =3D=3D 64)
+		r4k_blast_dcache_page_indexed =3D blast_dcache64_page_indexed;
 }
=20
 static void (* r4k_blast_dcache)(void);
@@ -138,6 +148,8 @@ static void __cpuinit r4k_blast_dcache_setup(void)
 		r4k_blast_dcache =3D blast_dcache16;
 	else if (dc_lsize =3D=3D 32)
 		r4k_blast_dcache =3D blast_dcache32;
+	else if (dc_lsize =3D=3D 64)
+		r4k_blast_dcache =3D blast_dcache64;
 }
=20
 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
--=20
1.5.3.6


