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From: David Daney <ddaney@caviumnetworks.com>
To: "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>,
	"ralf@linux-mips.org" <ralf@linux-mips.org>
CC: David Daney <ddaney@caviumnetworks.com>
Sender: "linux-mips-bounce@linux-mips.org" <linux-mips-bounce@linux-mips.org>
Date: Fri, 8 May 2009 12:52:10 -0700
Subject: [PATCH] MIPS: Don't write ones to reserved entryhi bits.
Thread-Topic: [PATCH] MIPS: Don't write ones to reserved entryhi bits.
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According to the MIPS64 Privileged Resource Architecture manual, only
values of zero may be written to bits 8..10 of CP0 entryhi.  We need
to add masking by ASID_MASK.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/include/asm/mmu_context.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mm=
u_context.h
index d7f3eb0..3899f99 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -169,7 +169,7 @@ static inline void switch_mm(struct mm_struct *prev, st=
ruct mm_struct *next,
 	ehb(); /* Make sure it propagates to TCStatus */
 	evpe(mtflags);
 #else
-	write_c0_entryhi(cpu_context(cpu, next));
+	write_c0_entryhi(cpu_context(cpu, next) & ASID_MASK);
 #endif /* CONFIG_MIPS_MT_SMTC */
 	TLBMISS_HANDLER_SETUP_PGD(next->pgd);
=20
@@ -229,7 +229,7 @@ activate_mm(struct mm_struct *prev, struct mm_struct *n=
ext)
 	ehb(); /* Make sure it propagates to TCStatus */
 	evpe(mtflags);
 #else
-	write_c0_entryhi(cpu_context(cpu, next));
+	write_c0_entryhi(cpu_context(cpu, next) & ASID_MASK);
 #endif /* CONFIG_MIPS_MT_SMTC */
 	TLBMISS_HANDLER_SETUP_PGD(next->pgd);
=20
--=20
1.6.0.6


