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From: David Daney <ddaney@caviumnetworks.com>
To: "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>,
	"ralf@linux-mips.org" <ralf@linux-mips.org>
CC: David Daney <ddaney@caviumnetworks.com>
Sender: "linux-mips-bounce@linux-mips.org" <linux-mips-bounce@linux-mips.org>
Date: Mon, 11 May 2009 12:11:02 -0700
Subject: [PATCH] MIPS: Remove execution hazard barriers for Octeon.
Thread-Topic: [PATCH] MIPS: Remove execution hazard barriers for Octeon.
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The Octeon has no execution hazards, so we can remove them and save an
instruction per TLB handler invocation.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/mm/tlbex.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 3548acf..4b2ea1f 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -257,7 +257,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, st=
ruct uasm_label **l,
 	case tlb_indexed: tlbw =3D uasm_i_tlbwi; break;
 	}
=20
-	if (cpu_has_mips_r2) {
+	if (cpu_has_mips_r2 && current_cpu_type() !=3D CPU_CAVIUM_OCTEON) {
 		uasm_i_ehb(p);
 		tlbw(p);
 		return;
--=20
1.6.0.6


