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From: David Daney <ddaney@caviumnetworks.com>
To: "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>,
	"ralf@linux-mips.org" <ralf@linux-mips.org>
CC: David Daney <ddaney@caviumnetworks.com>
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Date: Tue, 12 May 2009 12:41:54 -0700
Subject: [PATCH 2/3] MIPS: Remove execution hazard barriers for Octeon.
Thread-Topic: [PATCH 2/3] MIPS: Remove execution hazard barriers for Octeon.
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The Octeon has no execution hazards, so we can remove them and save an
instruction per TLB handler invocation.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides=
.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 04ce6e6..bb291f4 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -47,6 +47,7 @@
 #define cpu_has_mips32r2	0
 #define cpu_has_mips64r1	0
 #define cpu_has_mips64r2	1
+#define cpu_has_mips_r2_exec_hazard 0
 #define cpu_has_dsp		0
 #define cpu_has_mipsmt		0
 #define cpu_has_userlocal	0
--=20
1.6.0.6


