Received: from milmhbs1.lsil.com (147.145.21.209) by coscas01.lsi.com
 (172.21.36.60) with Microsoft SMTP Server id 8.1.393.1; Mon, 25 Jan 2010
 16:54:51 -0700
Received: from mail1.lsil.com (mail1.lsil.com [147.145.40.21])	by
 milmhbs1.lsil.com (8.12.11/8.12.11) with ESMTP id o0PNso8m021489	for
 <andy.sharp@lsi.com>; Mon, 25 Jan 2010 15:54:51 -0800
Received: from psmtp.com (na3sys009amx182.postini.com [74.125.149.163])	by
 mail1.lsil.com (8.12.11/8.12.11) with SMTP id o0PNsiPA005102	for
 <andy.sharp@lsi.com>; Mon, 25 Jan 2010 15:54:49 -0800 (PST)
Received: from source ([78.24.191.182]) by na3sys009amx182.postini.com
 ([74.125.148.14]) with SMTP;	Mon, 25 Jan 2010 18:54:49 EST
Received: from localhost.localdomain ([127.0.0.1]:36874 "EHLO
        eddie.linux-mips.org" rhost-flags-OK-OK-OK-FAIL)        by
 eddie.linux-mips.org with ESMTP id S2097177Ab0AYXy2 (ORCPT
        <rfc822;andy.sharp@lsi.com>); Tue, 26 Jan 2010 00:54:28 +0100
Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 26 Jan 2010 00:54:10
 +0100 (CET)
Received: from mail3.caviumnetworks.com ([12.108.191.235]:17822 "EHLO
        mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK)        by
 eddie.linux-mips.org with ESMTP id S2097174Ab0AYXyG (ORCPT
        <rfc822;linux-mips@linux-mips.org>); Tue, 26 Jan 2010 00:54:06 +0100
Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by
 mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378)        id
 <B4b5e2f210001>; Mon, 25 Jan 2010 15:54:09 -0800
Received: from caexch01.caveonetworks.com ([192.168.16.9]) by
 caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959);
         Mon, 25 Jan 2010 15:53:55 -0800
Received: from dd1.caveonetworks.com ([12.108.191.236]) by
 caexch01.caveonetworks.com over TLS secured channel with Microsoft
 SMTPSVC(6.0.3790.3959);         Mon, 25 Jan 2010 15:53:55 -0800
Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1])
        by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id o0PNro54009032;
        Mon, 25 Jan 2010 15:53:50 -0800
Received: (from ddaney@localhost)        by dd1.caveonetworks.com
 (8.14.2/8.14.2/Submit) id o0PNrnA2009030;        Mon, 25 Jan 2010 15:53:49
 -0800
From: David Daney <ddaney@caviumnetworks.com>
To: "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>,
	"ralf@linux-mips.org" <ralf@linux-mips.org>
CC: David Daney <ddaney@caviumnetworks.com>
Sender: "linux-mips-bounce@linux-mips.org" <linux-mips-bounce@linux-mips.org>
Date: Mon, 25 Jan 2010 16:53:49 -0700
Subject: [PATCH] MIPS: Decode c0_config4 for large TLBs.
Thread-Topic: [PATCH] MIPS: Decode c0_config4 for large TLBs.
Thread-Index: AcqeGckISV9hm7MNRymunGon+NIOXA==
Message-ID: <1264463629-9005-1-git-send-email-ddaney@caviumnetworks.com>
Accept-Language: en-US
Content-Language: en-US
X-MS-Exchange-Organization-AuthAs: Anonymous
X-MS-Exchange-Organization-AuthSource: coscas01.lsi.com
X-MS-Has-Attach:
X-Auto-Response-Suppress: All
X-MS-TNEF-Correlator:
x-scanned-by: MIMEDefang 2.39
errors-to: linux-mips-bounce@linux-mips.org
x-originalarrivaltime: 25 Jan 2010 23:53:55.0291 (UTC)
 FILETIME=[A75F92B0:01CA9E19]
x-pstn-levels: (S:99.90000/99.90000 CV:99.9000 FC:95.5390 LC:95.5390
 R:95.9108 P:95.9108 M:97.0282 C:98.6951 )
x-pstn-settings: 3 (1.0000:1.0000) s cv gt3 gt2 gt1 r p m c 
x-pstn-addresses: from <ddaney@caviumnetworks.com> [22/1] 
x-pstn-neptune: 0/0/0.00/0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0

For processors that have more than 64 TLBs, we need to decode both
config1 and config4 to determine the total number TLBs.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---

This is the second version, it uses more symbolic values and fewer
magic numbers.

 arch/mips/include/asm/mipsregs.h |    4 ++++
 arch/mips/kernel/cpu-probe.c     |   15 +++++++++++++++
 2 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsr=
egs.h
index 5c192a0..2cb1f0b 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -564,6 +564,10 @@
 #define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
 #define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
=20
+#define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)
+#define MIPS_CONF4_MMUEXTDEF	(_ULCAST_(3) << 14)
+#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
+
 #define MIPS_CONF7_WII		(_ULCAST_(1) << 31)
=20
 #define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 80e202e..b6a5c4a 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -691,6 +691,19 @@ static inline unsigned int decode_config3(struct cpuin=
fo_mips *c)
 	return config3 & MIPS_CONF_M;
 }
=20
+static inline unsigned int decode_config4(struct cpuinfo_mips *c)
+{
+	unsigned int config4;
+
+	config4 =3D read_c0_config4();
+
+	if ((config4 & MIPS_CONF4_MMUEXTDEF) =3D=3D MIPS_CONF4_MMUEXTDEF_MMUSIZEE=
XT
+	    && cpu_has_tlb)
+		c->tlbsize +=3D (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
+
+	return config4 & MIPS_CONF_M;
+}
+
 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 {
 	int ok;
@@ -709,6 +722,8 @@ static void __cpuinit decode_configs(struct cpuinfo_mip=
s *c)
 		ok =3D decode_config2(c);
 	if (ok)
 		ok =3D decode_config3(c);
+	if (ok)
+		ok =3D decode_config4(c);
=20
 	mips_probe_watch_registers(c);
 }
--=20
1.6.0.6


