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From: David Daney <ddaney@caviumnetworks.com>
To: "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>,
	"ralf@linux-mips.org" <ralf@linux-mips.org>
CC: David Daney <ddaney@caviumnetworks.com>
Sender: "linux-mips-bounce@linux-mips.org" <linux-mips-bounce@linux-mips.org>
Date: Wed, 10 Feb 2010 16:12:48 -0700
Subject: [PATCH 5/6] MIPS: Give Octeon+ CPUs their own cputype.
Thread-Topic: [PATCH 5/6] MIPS: Give Octeon+ CPUs their own cputype.
Thread-Index: AcqqptIIGPlqnAN2Ruiz3qgA/TfYmA==
Message-ID: <1265843569-5786-5-git-send-email-ddaney@caviumnetworks.com>
References: <4B733C71.8030304@caviumnetworks.com>
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This allows us to treat them differently at runtime.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/include/asm/cpu.h  |    2 +-
 arch/mips/kernel/cpu-probe.c |    6 +++++-
 arch/mips/mm/c-octeon.c      |    7 ++++---
 3 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index cf373a9..a5acda4 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -224,7 +224,7 @@ enum cpu_type_enum {
 	 * MIPS64 class processors
 	 */
 	CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
-	CPU_CAVIUM_OCTEON,
+	CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
=20
 	CPU_LAST
 };
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 9ea5ca8..ee67aac 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -162,6 +162,7 @@ void __init check_wait(void)
 	case CPU_BCM6348:
 	case CPU_BCM6358:
 	case CPU_CAVIUM_OCTEON:
+	case CPU_CAVIUM_OCTEON_PLUS:
 		cpu_wait =3D r4k_wait;
 		break;
=20
@@ -911,11 +912,14 @@ static inline void cpu_probe_cavium(struct cpuinfo_mi=
ps *c, unsigned int cpu)
 	case PRID_IMP_CAVIUM_CN38XX:
 	case PRID_IMP_CAVIUM_CN31XX:
 	case PRID_IMP_CAVIUM_CN30XX:
+		c->cputype =3D CPU_CAVIUM_OCTEON;
+		goto name_and_platform;
 	case PRID_IMP_CAVIUM_CN58XX:
 	case PRID_IMP_CAVIUM_CN56XX:
 	case PRID_IMP_CAVIUM_CN50XX:
 	case PRID_IMP_CAVIUM_CN52XX:
-		c->cputype =3D CPU_CAVIUM_OCTEON;
+		c->cputype =3D CPU_CAVIUM_OCTEON_PLUS;
+name_and_platform:
 		__cpu_name[cpu] =3D "Cavium Octeon";
 		if (cpu =3D=3D 0)
 			__elf_platform =3D "octeon";
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index af85959..0f9c488 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -183,6 +183,7 @@ static void __cpuinit probe_octeon(void)
=20
 	switch (c->cputype) {
 	case CPU_CAVIUM_OCTEON:
+	case CPU_CAVIUM_OCTEON_PLUS:
 		config1 =3D read_c0_config1();
 		c->icache.linesz =3D 2 << ((config1 >> 19) & 7);
 		c->icache.sets =3D 64 << ((config1 >> 22) & 7);
@@ -192,10 +193,10 @@ static void __cpuinit probe_octeon(void)
 			c->icache.sets * c->icache.ways * c->icache.linesz;
 		c->icache.waybit =3D ffs(icache_size / c->icache.ways) - 1;
 		c->dcache.linesz =3D 128;
-		if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
-			c->dcache.sets =3D 1; /* CN3XXX has one Dcache set */
-		else
+		if (c->cputype =3D=3D CPU_CAVIUM_OCTEON_PLUS)
 			c->dcache.sets =3D 2; /* CN5XXX has two Dcache sets */
+		else
+			c->dcache.sets =3D 1; /* CN3XXX has one Dcache set */
 		c->dcache.ways =3D 64;
 		dcache_size =3D
 			c->dcache.sets * c->dcache.ways * c->dcache.linesz;
--=20
1.6.2.5


