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From: David Daney <ddaney@caviumnetworks.com>
To: "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>,
	"ralf@linux-mips.org" <ralf@linux-mips.org>
CC: David Daney <ddaney@caviumnetworks.com>
Sender: "linux-mips-bounce@linux-mips.org" <linux-mips-bounce@linux-mips.org>
Date: Wed, 10 Feb 2010 16:12:49 -0700
Subject: [PATCH 6/6] MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+
 CPUs
Thread-Topic: [PATCH 6/6] MIPS: Enable Read Inhibit/eXecute Inhibit for
 Octeon+ CPUs
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Message-ID: <1265843569-5786-6-git-send-email-ddaney@caviumnetworks.com>
References: <4B733C71.8030304@caviumnetworks.com>
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Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides=
.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 425e708..bbf0540 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -58,6 +58,9 @@
 #define cpu_has_vint		0
 #define cpu_has_veic		0
 #define cpu_hwrena_impl_bits	0xc0000000
+
+#define kernel_uses_smartmips_rixi (cpu_data[0].cputype =3D=3D CPU_CAVIUM_=
OCTEON_PLUS)
+
 #define ARCH_HAS_READ_CURRENT_TIMER 1
 #define ARCH_HAS_IRQ_PER_CPU	1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1
--=20
1.6.2.5


