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Date: Sun, 14 Oct 2007 18:58:44 -0700
From: Andrew Sharp <andy.sharp@onstor.com>
To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: paging problem with ide-cs driver
Message-ID: <20071014185844.2ea76a22@ripper.onstor.net>
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On Sat, 13 Oct 2007 00:38:48 +0100 Ralf Baechle <ralf@linux-mips.org>
wrote:

> On Fri, Oct 12, 2007 at 03:23:21PM -0700, Andrew Sharp wrote:
> 
> > On Wed, 10 Oct 2007 17:30:32 +0100 Ralf Baechle
> > <ralf@linux-mips.org> wrote:
> > 
> > > On Wed, Oct 10, 2007 at 07:50:41AM -0700, Andrew Sharp wrote:
> > > 
> > > > > (As collateral damage 06e523e89ec0322c4abcf41533d5380dfcd81f73
> > > > > breaks support for pass 1 BCM1250 parts.  But it seems I'm the
> > > > > last one with one of those ...)

OK, I ported my changes forward to that commit and it's still no go.
Attached is the patch of my changes -- I have to fix the
rscs_nonstatic.c in drivers/pcmcia to work with non-x86 and a few
touch-ups to the pci-sb1250.c file -- you might want to take a look at
the changes I made to get the paging code to compile in 64-bit mode.
Could be some bogus hacks in there.

> My pass 1 machine is only running stable at 450MHz.  I received it
> set to 500MHz and also tried 550MHz and 400MHz but only 450MHz is
> stable.

<immediately whips out a screwdriver and starts mucking with his swarms

> Well, the commit in question 641e97f318870921d048154af6807e46e43c307a.

I don't seem to know what that is.

Cheers,

a

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diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 90b409d..20daa8c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -52,8 +52,8 @@ config BCM47XX
 	select SYS_HAS_CPU_MIPS32_R1
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_LITTLE_ENDIAN
-	select SSB
-	select SSB_DRIVER_MIPS
+#	select SSB
+#	select SSB_DRIVER_MIPS
 	select GENERIC_GPIO
 	help
 	 Support for BCM47XX based boards
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index e46782b..58d5ce5 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -147,6 +147,8 @@ EXPORT(_stext)
 	 * not have a ELF loader yet.
 	 */
 	__INIT
+#else
+	j kernel_entry
 #endif
=20
 NESTED(kernel_entry, 16, sp)			# kernel entry point
@@ -198,7 +200,9 @@ NESTED(kernel_entry, 16, sp)			# kernel entry point
 	j		start_kernel
 	END(kernel_entry)
=20
+#ifdef CONFIG_BOOT_RAW
 	__INIT
+#endif
=20
 #ifdef CONFIG_SMP
 /*
diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c
index 82f42ac..3c0cc73 100644
--- a/arch/mips/mm/pg-sb1.c
+++ b/arch/mips/mm/pg-sb1.c
@@ -216,7 +216,8 @@ void sb1_dma_init(void)
 	int i;
=20
 	for (i =3D 0; i < DM_NUM_CHANNELS; i++) {
-		const u64 base_val =3D CPHYSADDR(&page_descr[i]) |
+		u32 pd_32 =3D _ACAST32_ ((u64)&page_descr[i] & 0xffffffffUL);
+		const u64 base_val =3D (u64)(CPHYSADDR(pd_32)) |
 				     V_DM_DSCR_BASE_RINGSZ(1);
 		void *base_reg =3D IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
=20
@@ -228,11 +229,12 @@ void sb1_dma_init(void)
=20
 void clear_page(void *page)
 {
-	u64 to_phys =3D CPHYSADDR(page);
 	unsigned int cpu =3D smp_processor_id();
+	u32 page32 =3D _ACAST32_ ((u64)page & 0xffffffffUL);
+	u64 to_phys =3D (u64)CPHYSADDR(page32);
=20
 	/* if the page is not in KSEG0, use old way */
-	if ((long)KSEGX(page) !=3D (long)CKSEG0)
+	if ((long)KSEGX(page32) !=3D (long)CKSEG0)
 		return clear_page_cpu(page);
=20
 	page_descr[cpu].dscr_a =3D to_phys | M_DM_DSCRA_ZERO_MEM |
@@ -252,13 +254,15 @@ void clear_page(void *page)
=20
 void copy_page(void *to, void *from)
 {
-	u64 from_phys =3D CPHYSADDR(from);
-	u64 to_phys =3D CPHYSADDR(to);
 	unsigned int cpu =3D smp_processor_id();
+	u32 from32 =3D _ACAST32_ ((u64)from & 0xffffffffUL);
+	u32 to32 =3D _ACAST32_ ((u64)to & 0xffffffffUL);
+	u64 from_phys =3D CPHYSADDR(from32);
+	u64 to_phys =3D CPHYSADDR(to32);
=20
 	/* if any page is not in KSEG0, use old way */
-	if ((long)KSEGX(to) !=3D (long)CKSEG0
-	    || (long)KSEGX(from) !=3D (long)CKSEG0)
+	if ((long)KSEGX(to32) !=3D (long)CKSEG0
+	    || (long)KSEGX(from32) !=3D (long)CKSEG0)
 		return copy_page_cpu(to, from);
=20
 	page_descr[cpu].dscr_a =3D to_phys | M_DM_DSCRA_L2C_DEST |
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index c1ac649..f1ab391 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -42,7 +42,7 @@
=20
 #include <asm/sibyte/sb1250_defs.h>
 #include <asm/sibyte/sb1250_regs.h>
-#include <asm/sibyte/sb1250_scd.h>
+#include <asm/sibyte/sb1250.h>
 #include <asm/sibyte/board.h>
=20
 /*
@@ -84,10 +84,12 @@ static inline void WRITECFG32(u32 addr, u32 data)
 	*(u32 *) (cfg_space + (addr & ~3)) =3D data;
 }
=20
+#ifdef CONFIG_SIBYTE_CFE
 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
 	return dev->irq;
 }
+#endif
=20
 /* Do platform specific device initialization at pci_enable_device() time =
*/
 int pcibios_plat_dev_init(struct pci_dev *dev)
@@ -187,7 +189,11 @@ struct pci_ops sb1250_pci_ops =3D {
=20
 static struct resource sb1250_mem_resource =3D {
 	.name	=3D "SB1250 PCI MEM",
+#ifdef CONFIG_ISA
 	.start	=3D 0x40000000UL,
+#else
+	.start	=3D 0x41000000UL,
+#endif
 	.end	=3D 0x5fffffffUL,
 	.flags	=3D IORESOURCE_MEM,
 };
@@ -203,20 +209,25 @@ struct pci_controller sb1250_controller =3D {
 	.pci_ops	=3D &sb1250_pci_ops,
 	.mem_resource	=3D &sb1250_mem_resource,
 	.io_resource	=3D &sb1250_io_resource,
+	.io_map_base	=3D -1UL,
 };
=20
 static int __init sb1250_pcibios_init(void)
 {
 	uint32_t cmdreg;
 	uint64_t reg;
+#ifdef CONFIG_SIBYTE_CFE
 	extern int pci_probe_only;
=20
 	/* CFE will assign PCI resources */
 	pci_probe_only =3D 1;
+#endif
=20
 	/* Avoid ISA compat ranges.  */
 	PCIBIOS_MIN_IO =3D 0x00008000UL;
+#ifdef CONFIG_ISA
 	PCIBIOS_MIN_MEM =3D 0x01000000UL;
+#endif
=20
 	/* Set I/O resource limits.  */
 	ioport_resource.end =3D 0x01ffffffUL;	/* 32MB accessible by sb1250 */
@@ -232,13 +243,10 @@ static int __init sb1250_pcibios_init(void)
 	if (!(reg & M_SYS_PCI_HOST)) {
 		sb1250_bus_status |=3D PCI_DEVICE_MODE;
 	} else {
-		cmdreg =3D
-		    READCFG32(CFGOFFSET
-			      (0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
+		cmdreg =3D READCFG32(CFGOFFSET (0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
 			       PCI_COMMAND));
 		if (!(cmdreg & PCI_COMMAND_MASTER)) {
-			printk
-			    ("PCI: Skipping PCI probe.  Bus is not initialized.\n");
+			printk("PCI: Skipping PCI probe.  Bus is not initialized.\n");
 			iounmap(cfg_space);
 			return 0;
 		}
@@ -256,8 +264,13 @@ static int __init sb1250_pcibios_init(void)
=20
 	set_io_port_base((unsigned long)
 			 ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536));
+	/*
+	 * ioremap the PCI Memory IO space for legacy ISA or southbridge PCI.
+	 */
+#ifdef CONFIG_ISA
 	isa_slot_offset =3D (unsigned long)
-	    ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024);
+	    ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 16 * 1024 * 1024);
+#endif
=20
 #ifdef CONFIG_SIBYTE_HAS_LDT
 	/*
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index fdd7bd9..0904f7e 100644
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -49,7 +49,6 @@ config SIBYTE_BCM1x55
 config SIBYTE_SB1xxx_SOC
 	bool
 	select DMA_COHERENT
-	select SIBYTE_CFE
 	select SWAP_IO_SPACE
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_64BIT_KERNEL
@@ -124,6 +123,7 @@ config SB1_CERR_STALL
 config SIBYTE_CFE
 	bool "Booting from CFE"
 	depends on SIBYTE_SB1xxx_SOC
+	default y if SIBYTE_SB1xxx_SOC
 	select SYS_HAS_EARLY_PRINTK
 	help
 	  Make use of the CFE API for enumerating available memory,
diff --git a/drivers/pcmcia/rsrc_nonstatic.c b/drivers/pcmcia/rsrc_nonstati=
c.c
index bfcaad6..c4fe8a3 100644
--- a/drivers/pcmcia/rsrc_nonstatic.c
+++ b/drivers/pcmcia/rsrc_nonstatic.c
@@ -737,8 +737,10 @@ static int adjust_io(struct pcmcia_socket *s, unsigned=
 int action, unsigned long
 	if (end < start)
 		return -EINVAL;
=20
+#ifndef CONFIG_MIPS
 	if (end > IO_SPACE_LIMIT)
 		return -EINVAL;
+#endif
=20
 	mutex_lock(&rsrc_mutex);
 	switch (action) {

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