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Date: Wed, 19 Nov 2008 14:15:36 -0800
From: Andrew Sharp <andy.sharp@onstor.com>
To: Bill Fisher <bfisher@onstor.com>
Cc: Brian Stark <brian.stark@onstor.com>
Subject: Re: BCM 1480 Mailbox Register Address'es and Offset
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These are the kind of details best left to me -- worry your pretty
little head about the networking code.  I'll make sure the system crap
works as needed.

On Wed, 19 Nov 2008 13:44:46 -0800 Bill Fisher <bfisher@onstor.com>
wrote:

> Brian Stark wrote:
> > Bill,
> > 
> > I wouldn't change A_BCM1480_IMR_CPU0_BASE as this is the address
> > the TXRX uses to get at his own mailbox registers.  
> > 
> > There should be a #define in the 1125 kernel that targets the TXRX
> > and FP mailboxes.  I assume it would be defined with macros similar
> > to the ones that created the TXRX->SSC physical address (0x10 7000
> > 0008).  
> > 
> > There just needs to be similar macros for the SSC->TXRX direction
> > in the 1125 kernel that would create the physical address that
> > you're proposing:
> > 
> > 0xF880000008UL
> > 
> > 
> > 
> I agree. ON the SSC the mgmt_bus device driver's interrupt handler is 
> "registered" via a call to request_irq(), as per the following code:
> 
> > int
> > mgmtbus_irq_setup(struct net_device *dev)
> > {
> >     int ret;
> > 
> >     ret = request_irq(K_INT_MBOX_3, mgmtbus_mailbox_intr,
> >                       IRQF_SHARED, dev->name, dev);
> >     if (ret) {
> >         printk(KERN_ERR "%s: can't register irq %d: %d\n",
> > __FUNCTION__, K_INT_MBOX_3, ret);
> >     } else {
> >        printk(KERN_INFO "MGMTBUS: using irq %d\n", K_INT_MBOX_3);
> >     }
> >     return ret;
> > }
> 
> The actual handler is:
> 
> > static irqreturn_t
> > mgmtbus_mailbox_intr(int irq, void *dev_id)
> > {
> >     /* Acknowledge the interrupt by clearing the mailbox */
> >     *(uint64_t *)PHYS_TO_XKSEG_UNCACHED(
> >         A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)) = 0xFFFFUL;
> > 
> >    mgmtbus_intr(1 << MGMTBUS_ADDR_TXRX);
> >    return IRQ_HANDLED;
> > }
> 
> The value of K_INT_MBOX_3 is defined in 
> include/asm-mips/sibyte/sb1250_int.h and
> have the value(s):
> 
> #define K_INT_MBOX_0                26
> #define K_INT_MBOX_1                27
> #define K_INT_MBOX_2                28
> #define K_INT_MBOX_3                29
> 
> Hence writing the 0xFFFF into the low 16-bits of the
> interrupt mailbox location on the TxRx at is the
> trigger for mailbox 3 on the SSC.
> 
> There does NOT appear to be any major changes to the
> files, which is what I suspected; The changes are:
> 
> bfisher-linux:bfisher 985>p4 diff sb1250_int.h#2 sb1250_int.h#1
> sb1250_int.h#2 - file(s) up-to-date.
> ==== 
> //depot/dev/linux/kernel/linux-mips-2.6/include/asm-mips/sibyte/sb1250_int.h#1 
> - 
> /homes/bfisher/work/fisher-W1-dev/dev/linux/kernel/linux-mips-2.6/include/asm-mips/sibyte/sb1250_int.h 
> ====
> 48,49d47
> < #if SIBYTE_HDR_FEATURE_1250_112x
> <
> 154a153
>  > #define M_INT_MBOX_ALL              _SB_MAKEMASK(4,K_INT_MBOX_0)
> 250,251d248
> <
> < #endif
> 
> Hence, what I'm missing is the setup code that maps the
> TxRX physical address 0x1070000008UL into the
> proper mailbox virtual address on the SSC?
> 
> As Andy says, this might be going to too much detail.
> 
> Thanks,
> 
