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Date: Fri, 19 Dec 2008 18:52:14 -0800
From: Andrew Sharp <andy.sharp@onstor.com>
To: Bill Fisher <bfisher@onstor.com>
Subject: Re: TxRx and SSC Mailbox Interrupts
Message-ID: <20081219185214.76ef1f74@ripper.onstor.net>
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On Tue, 16 Dec 2008 11:39:24 -0800 Bill Fisher <bfisher@onstor.com>
wrote:

> Brian:
> 
> Now that I have a mgmt bus device driver running
> on the 1480 hardware, I need to get the interrupts
> working in both directions in order to get
> the packet transmit interrupts working.
> 
> On the TxRx under EEE, the following location
> is used to generate Mailbox 3 interrupt on the SSC.
> 
> /* The register type. */
> #define MGMTBUS_SSC_INTERRUPT_REG_SIZE uint64_t
> 
> /*
>   * This TXRX PCI write generates a SSC mailbox interrupt.
>   * The TXRX physical PCI address MUST have 0x10 in top 8-bits,
>   * Location of mailbox register to generate interrupt on SSC from
> TXRX.
>   * The 1125 "mailbox set" register accessed through PCI BAR2.
>   */
> #define MGMTBUS_SSC_INTERRUPT_REG
> PHYS_TO_XKSEG_UNCACHED(0x1070000008UL)
> 
> /* The value to write to the register. Generates MBOX_INT_3 on the
> 1125 */ #define MGMTBUS_SSC_INTERRUPT_VAL 0xFFFFUL
> 
> 1) The PCI mapping will probably have to be setup for
>     this location on the TxRx Linux.
> 
> 2) What is the "magic" location(s) on the SSC to create
>     a corresponding Mailbox interrupt on the TxRx?
> 
> 3) I am presuming the TxRx PROM code initializes the map for the
>     location 0x1070000008UL, do you remember this?
>     I will check out the PROM code to be sure.

Everything I sent before I believe is correct, and the interrupt number
that you should register the driver to on the tuxrx side is

K_BCM1480_INT_MBOX_0_3

