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Date: Tue, 8 May 2007 09:42:24 -0700
From: Andrew Sharp <andy.sharp@onstor.com>
To: "Brian Stark" <brian.stark@onstor.com>
Cc: "Warren Gale" <warren.gale@onstor.com>
Subject: Re: assignments & settings for TI part
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I think I stated exactly what documentation I'm looking for, didn't
I?  The email snippets quoted here would highly suggest that in fact it
does not work exactly like the other part, so I don't know why you keep
saying that.  Maybe I don't understand something, but it sounds like
the interrupts are reversed, and the part does request PCI MEM
resources, unlike the Cirrus part, so that's different too.

Am I being dense?  I know I'm just an ignorant software engineer, so
help me out here.

a

On Tue, 8 May 2007 09:15:18 -0700 "Brian Stark"
<brian.stark@onstor.com> wrote:

> Andy,
> 
> What kind of documentation are you looking for?  The part works just
> like the old one, and we can change that if needed.
> 
> 
> Brian
> 
> 
> -----Original Message-----
> From: Andy Sharp
> To: Warren Gale
> CC: Brian Stark
> Sent: Tue May 08 08:29:48 2007
> Subject: Re: assignments & settings for TI part
> 
> Whipping out my French/English dictionary, I find that I cannot
> translate any of this.  Darn.
> 
> So, what I'm hearing is that we don't have this properly documented
> anywhere, and in BSD just the bare minimum was done to make it use the
> pd6729 driver in compatibility mode, with the same performance
> deficiencies.
> 
> I did try swapping the irqs and using irq11 for slot 1 and irq10 for
> slot 2, but that gave the same results.  Just in case the French
> words below were saying I should do that.
> 
> On Mon, 7 May 2007 18:19:41 -0700 "Warren Gale"
> <warren.gale@onstor.com> wrote:
> 
> > Andy,
> >   Dan did some changes that are in BSD drivers for the TI Part.
> > If I remember right we look at the ID and do some different stuff
> > depending on which part is there...
> > 
> > 
> > There was something in an e-mail thread about interrupts.
> >  > Dan, the TI controller can only map socket A interrupts to INTA_L
> >  > and
> > 
> >  > socket B interrupts to INTB_L.  This is basically reversed from
> >  > the old Bobcat since we program the Intel controller to generate
> >  > socket A
> > 
> >  > interrupts on PCI INTB_L / PMC INT8_L and socket B interrupts on
> >  > PCI INTA_L / PMC INT9_L.  On the new board, we have to reverse
> >  > the interrupts inside the PMC.  Can you build a BSD image that
> >  > looks for socket A interrupts on PCI INTA_L / PMC INT9_L (IM11)
> >  > and socket B interrupts on PCI INTB_L / PMC INT8_L (IM10)?
> >  >
> > 
> > Here is the change list numbers and the files Dan modified to 
> > get it to work with BSD.
> > 
> > 
> > Change List #'s  21194, 21246
> > 
> > Files:
> > //depot/R1_3_3_work/openbsd/src/sys/arch/pmonmips/pci/pcic_pci_machdep.c
> > #4 edit
> > //depot/R1_3_3_work/openbsd/src/sys/arch/pmonmips/pmonmips/kgdb_machdep.
> > c#4 edit
> > //depot/R1_3_3_work/openbsd/src/sys/arch/pmonmips/pmonmips/machdep.c#4
> > edit
> > //depot/R1_3_3_work/openbsd/src/sys/dev/ic/i82365.c#4 edit
> > //depot/R1_3_3_work/openbsd/src/sys/dev/pci/i82365_pci.c#4 edit
> > //depot/R1_3_3_work/openbsd/src/sys/dev/pci/pci.c#4 edit
> > //depot/R1_3_3_work/openbsd/src/sys/dev/pci/pcidevs.h#4 edit
> > //depot/R1_3_3_work/openbsd/src/sys/dev/pci/pcidevs_data.h#4 edit
> > 
> > Hope this helps :)
> > Warren
> > 
> > -----Original Message-----
> > From: Brian Stark 
> > Sent: Monday, May 07, 2007 5:27 PM
> > To: Andy Sharp
> > Cc: Warren Gale
> > Subject: Re: assignments & settings for TI part
> > 
> > Andy,
> > 
> > The mem map and interrupts are configured in prom and are set up
> > identically to the Intel part.  Let me dig through some old emails
> > to see if Dan did anything differently in bsd.  If not, then prom
> > will serve as the best example, and Warren can help answer
> > questions.
> > 
> > 
> > Brian
> > 
> > 
> > 
> > -----Original Message-----
> > From: Andy Sharp
> > To: Brian Stark
> > Sent: Mon May 07 17:05:10 2007
> > Subject: assignments & settings for TI part
> > 
> > Hi B,
> > 
> > Thanks for the Data Manual on the TI part, but I really need to know
> > how it is configured for use in bobcat.  Ala the info in the memory
> > map document, except for the TI part.  What IRQs should be used for
> > what sockets and memory assignments and so forth.
> > 
> > Cheers,
> > 
> > a
