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Date: Tue, 30 Mar 2010 13:55:03 -0700
From: Andrew Sharp <andy.sharp@lsi.com>
To: "Kozlovsky, Maxim" <Maxim.Kozlovsky@lsi.com>
Subject: Re: cache aliasing
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On Tue, 30 Mar 2010 14:44:59 -0600 "Kozlovsky, Maxim"
<Maxim.Kozlovsky@lsi.com> wrote:

> Txrx accesses the memory cacheable. One party accessing the memory
> cacheable is enough to create aliasing problem. 

But that's not an aliasing problem it's just a synchronizing problem.
Read that whole section starting on that page, you'll see what I mean.

> -----Original Message-----
> From: Andrew Sharp [mailto:andy.sharp@lsi.com] 
> Sent: Tuesday, March 30, 2010 1:38 PM
> To: Kozlovsky, Maxim
> Subject: Re: cache aliasing
> 
> On Tue, 30 Mar 2010 14:20:55 -0600 "Kozlovsky, Maxim"
> <Maxim.Kozlovsky@lsi.com> wrote:
> 
> > Page 36,
> > 
> > Cache coherency is not maintained between accesses to the same
> > resource from the two different address spaces...Cacheable accesses
> > must be done through only one region to maintain coherency. If this
> > is not done, two copies of a particular cache line can be present in
> > any cache at any time...
> > 
> > ...
> > 
> > If a resource is generally shared (coherently or not) , the upper
> > alias should be used.
> > 
> 
> Yeah, of course, but the key word is "cacheable".  See page 329.
> 
> "IO devices on the ZBbus never do cacheable coherent requests to
> remote addresses. Instead, they are mapped to UC reads and writes,
> which get translated to IO commands. Although a device could
> functrion correctly using coherent commands, the latency and
> bandwidth for writes is greatly reduced."
> 
> In the case you're talking about, there's no code running on the FP.
> 
