AF:
NF:0
PS:10
SRH:1
SFN:
DSR:
MID:
CFG:
PT:0
S:andy.sharp@lsi.com
RQ:
SSV:mhbs.lsil.com
NSV:
SSH:
R:<Maxim.Kozlovsky@lsi.com>
MAID:2
X-Sylpheed-Privacy-System:
X-Sylpheed-Sign:0
SCF:#mh/Mailbox/sent
RMID:#imap/LSI/INBOX	0	861DA0537719934884B3D30A2666FECC010E4407D7@cosmail02.lsi.com
X-Sylpheed-End-Special-Headers: 1
Date: Tue, 30 Mar 2010 14:04:29 -0700
From: Andrew Sharp <andy.sharp@lsi.com>
To: "Kozlovsky, Maxim" <Maxim.Kozlovsky@lsi.com>
Subject: Re: cache aliasing
Message-ID: <20100330140429.686991ab@ripper.onstor.net>
In-Reply-To: <861DA0537719934884B3D30A2666FECC010E4407D7@cosmail02.lsi.com>
References: <861DA0537719934884B3D30A2666FECC010E440781@cosmail02.lsi.com>
	<20100330133752.5883b463@ripper.onstor.net>
	<861DA0537719934884B3D30A2666FECC010E4407C2@cosmail02.lsi.com>
	<20100330135503.5ee0b7ea@ripper.onstor.net>
	<861DA0537719934884B3D30A2666FECC010E4407D7@cosmail02.lsi.com>
Organization: LSI
X-Mailer: Sylpheed-Claws 2.6.0 (GTK+ 2.8.20; x86_64-pc-linux-gnu)
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: 7bit

On Tue, 30 Mar 2010 14:58:20 -0600 "Kozlovsky, Maxim"
<Maxim.Kozlovsky@lsi.com> wrote:

> I don't know what you mean by synchronizing problem. Of course it is
> aliasing problem.
> 
> Txrx writes cacheline at low alias, then qlogic accesses the same
> address at high alias, the memory controller checks the cache and
> finds nothing there because the cache contains the low alias, so
> wrong data gets to qlogic. 

Oh come on.  Anything you are writing to disk should be written to FP
local memory, no?  Anything else should be written with non-cached
address.

> -----Original Message-----
> From: Andrew Sharp [mailto:andy.sharp@lsi.com] 
> Sent: Tuesday, March 30, 2010 1:55 PM
> To: Kozlovsky, Maxim
> Subject: Re: cache aliasing
> 
> On Tue, 30 Mar 2010 14:44:59 -0600 "Kozlovsky, Maxim"
> <Maxim.Kozlovsky@lsi.com> wrote:
> 
> > Txrx accesses the memory cacheable. One party accessing the memory
> > cacheable is enough to create aliasing problem. 
> 
> But that's not an aliasing problem it's just a synchronizing problem.
> Read that whole section starting on that page, you'll see what I mean.
> 
> > -----Original Message-----
> > From: Andrew Sharp [mailto:andy.sharp@lsi.com] 
> > Sent: Tuesday, March 30, 2010 1:38 PM
> > To: Kozlovsky, Maxim
> > Subject: Re: cache aliasing
> > 
> > On Tue, 30 Mar 2010 14:20:55 -0600 "Kozlovsky, Maxim"
> > <Maxim.Kozlovsky@lsi.com> wrote:
> > 
> > > Page 36,
> > > 
> > > Cache coherency is not maintained between accesses to the same
> > > resource from the two different address spaces...Cacheable
> > > accesses must be done through only one region to maintain
> > > coherency. If this is not done, two copies of a particular cache
> > > line can be present in any cache at any time...
> > > 
> > > ...
> > > 
> > > If a resource is generally shared (coherently or not) , the upper
> > > alias should be used.
> > > 
> > 
> > Yeah, of course, but the key word is "cacheable".  See page 329.
> > 
> > "IO devices on the ZBbus never do cacheable coherent requests to
> > remote addresses. Instead, they are mapped to UC reads and writes,
> > which get translated to IO commands. Although a device could
> > functrion correctly using coherent commands, the latency and
> > bandwidth for writes is greatly reduced."
> > 
> > In the case you're talking about, there's no code running on the FP.
> > 
